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MC100LVEL12DG Datasheet

  • MC100LVEL12DG

  • ON Semiconductor [3.3V ECL Low Impedance Driver]

  • ONSEMI

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MC100EPT24
3.3V LVTTL/LVCMOS to
Differential LVECL Translator
Description
The MC100EPT24 is a LVTTL/LVCMOS to differential LVECL
translator. Because LVECL levels and LVTTL/LVCMOS levels are
used, a
鈭?.3
V, +3.3 V and ground are required. The small outline
8鈭抣ead package and the single gate of the EPT24 makes it ideal for
those applications where space, performance, and low power are at a
premium.
Features
8
1
http://onsemi.com
MARKING DIAGRAMS*
8
SOIC鈭?
D SUFFIX
CASE 751
1
8
8
1
TSSOP鈭?
DT SUFFIX
CASE 948R
1
DFN8
MN SUFFIX
CASE 506AA
KA24
ALYWG
G
KPT24
ALYW
G
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
1
A
L
Y
W
M
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Date Code
= Pb鈭扚ree Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
漏
Semiconductor Components Industries, LLC, 2006
December, 2006
鈭?/div>
Rev. 8
1
Publication Order Number:
MC100EPT24/D
3U MG
G
4
350 ps Typical Propagation Delay
Maximum Input Clock Frequency > 1.0 GHz Typical
The 100 Series Contains Temperature Compensation
Operating Range: V
CC
= 3.0 V to 3.6 V;
V
EE
=
鈭?.6
V to
鈭?.0
V; GND = 0 V
鈥?/div>
PNP LVTTL Input for Minimal Loading
鈥?/div>
Q Output will Default HIGH with Input Open
鈥?/div>
Pb鈭扚ree Packages are Available

MC100LVEL12DG PDF文件相關(guān)型號(hào)

MC100LVEL12DR2G,MC100LVEL12DTG,MC100LVEL12DTR2G,MC100LVEL12MNR4

MC100LVEL12DG 產(chǎn)品屬性

  • 98

  • 集成電路 (IC)

  • 邏輯 - 緩沖器，驅(qū)動(dòng)器，接收器，收發(fā)器

  • 100LVEL

  • 緩沖器/線路驅(qū)動(dòng)器，非反相

  • 1

  • 1

  • -

  • 3 V ~ 3.8 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 8-SOIC（0.154"，3.90mm 寬）

  • 8-SOICN

  • 管件

  • MC100LVEL12DGOS

MC100LVEL12DG相關(guān)型號(hào)PDF文件下載

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