MC100LVE222
3.3 V/5.0 V ECL 1:15
Differential
梅1/梅2
Clock Driver
The MC100LVE222 is a low skew 1:15 differential
梅1/梅2
ECL
fanout buffer designed with clock distribution in mind. The
LVECL/LVPECL input signal pairs can be differential or used
single鈭抏nded (with V
BB
output reference bypassed and connected to the
unused input of a pair). Either of two fully differential clock inputs may
be selected. Each of the four output banks of 2, 3, 4, and 6 differential
pairs may be indwependently configured to fanout 1X or 1/2X of the
input frequency. The LVE222 specifically guarantees low output to
output skew. Optimal design, layout, and processing minimize skew
within a device and from lot to lot.
The fsel pins and CLK_Sel pin are asynchronous control inputs. Any
changes may cause indeterminate output states requiring an MR pulse
to resynchronize any 1/2X outputs.
The device tpd is affected by the quantity of output pairs terminated
with a minimum occurring with only one output pair and increasing
about 10鈭?0 ps for all output pairs. Relative skew distribution is not
affected as more pairs are terminated, but the increased tpd does shift
the entire distribution. Unused output pairs should be left unterminated
(open) to reduce power and switching noise.
The MC100LVE222, as with most ECL devices, can be operated
from a positive V
CC
/V
CCO
supply in PECL mode. This allows the
LVE222 to be used for high performance clock distribution in +3.3 V
systems. Operation with >3.8
|(V
CC
or V
CCO
鈭扸
EE
|
span will require
special thermal handling considerations. Designers can take advantage
of the LVE222鈥檚 performance to distribute low skew clocks across the
backplane or the board. In a PECL environment series or Thevenin line,
terminations are typically used as they require no additional power
supplies. All power supply pins must be connected. For more
information on using PECL, designers should refer to Application Note
AN1406/D. For a SPICE model, refer to Application Note AN1560/D.
http://onsemi.com
MARKING DIAGRAM*
LQFP
FA SUFFIX
CASE 848D
MC100LVE
222
AWLYYWWG
52
1
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb鈭扚ree Package
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
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200 ps Part鈭抰o鈭扨art Skew
50 ps Output鈭抰o鈭扥utput Skew
Selectable 1x or 1/2x Frequency Outputs
ESD Protection: >2 kV HBM, >200 V MM
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: V
CC
/V
CCO
= 3.0 V to 5.25 V with
V
EE
= 0 V
NECL Mode Operating Range: V
CC
/V
CCO
= 0 V with V
EE
= 鈭?.0 V
to 鈭?.25 V
Internal Input Pulldown Resistors
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 2
For Additional Information, refer to Application Note AND8003/D
Flammability Rating: UL 94 V鈭? @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 684 devices
Pb鈭扚ree Packages are Available*
*For additional information on our Pb鈭扚ree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
漏
Semiconductor Components Industries, LLC, 2005
1
October, 2005鈭?Rev. 11
Publication Order Number:
MC100LVE222/D
MC100LVE222FAG PDF文件相關(guān)型號(hào)
MC100LVE222FAR2G
MC100LVE222FAG 產(chǎn)品屬性
MC100LVE222FAG相關(guān)型號(hào)PDF文件下載
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