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MC100EP809FAG Datasheet

  • MC100EP809FAG

  • ON Semiconductor [3.3V 1:9 Differential HSTL/PECL to HSTL C...

  • ONSEMI

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MC100EP809
3.3V 1:9 Differential
HSTL/PECL to HSTL Clock
Driver with LVTTL Clock
Select and Enable
Description
http://onsemi.com
MARKING
DIAGRAM*
The MC100EP809 is a low skew 1鈭抰o鈭? differential clock driver,
designed with clock distribution in mind, accepting two clock sources into
an input multiplexer. The part is designed for use in low voltage
applications which require a large number of outputs to drive precisely
aligned low skew signals to their destination. The two clock inputs are
differential HSTL or PECL and they are selected by the CLK_SEL pin
which is LVTTL. To avoid generation of a runt clock pulse when the
device is enabled/disabled, the Output Enable (OE), which is LVTTL, is
synchronous ensuring the outputs will only be enabled/disabled when they
are already in LOW state (Figure 8).
The MC100EP809 guarantees low output鈭抰o鈭抩utput skew. The optimal
design, layout, and processing minimize skew within a device and from lot
to lot. The MC100EP809 output structure uses open emitter architecture
and will be terminated with 50
W
to ground instead of a standard HSTL
configuration (Figure 6). To ensure the tight skew specification is realized,
both sides of the differential output need to be terminated identically into
50
W
even if only one output is being used. If an output pair is unused,
both outputs may be left open (unterminated) without affecting skew.
Designers can take advantage of the EP809鈥檚 performance to
distribute low skew clocks across the backplane of the board. HSTL
clock inputs may be driven single鈭抏nd by biasing the non鈭抎riven pin
in an input pair (Figure 7).
Features
MC100
EP809
32鈭扡EAD LQFP
FA SUFFIX
CASE 873A
AWLYYWWG
32
1
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb鈭扚ree Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
鈥?/div>
100 ps Typical Device鈭抰o鈭扗evice Skew
鈥?/div>
15 ps Typical within Device Skew
鈥?/div>
HSTL Compatible Outputs Drive 50
W
to GND with no
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Offset Voltage
Maximum Frequency
>
750 MHz
850 ps Typical Propagation Delay
Fully Compatible with Micrel SY89809L
PECL and HSTL Mode Operating Range: V
CCI
= 3 V to 3.6 V
with GND = 0 V, V
CCO
= 1.6 V to 2.0 V
Open Input Default State
Pb鈭扚ree Packages are Available
漏
Semiconductor Components Industries, LLC, 2006
November, 2006
鈭?/div>
Rev. 7
1
Publication Order Number:
MC100EP809/D

MC100EP809FAG 產(chǎn)品屬性

  • 250

  • 集成電路 (IC)

  • 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器，驅(qū)動(dòng)器

  • 100EP

  • 扇出緩沖器（分配），多路復(fù)用器

  • 2

  • 1:9

  • 是/是

  • HSTL，LVDS，LVPECL

  • HSTL

  • 750MHz

  • 3 V ~ 3.6 V

  • 0°C ~ 85°C

  • 表面貼裝

  • 32-LQFP

  • 32-LQFP（7x7）

  • 托盤(pán)

  • MC100EP809FAGOS

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