MC100EL39
5V ECL
梅2/4, 梅4/6
Clock
Generation Chip
The MC100EL39 is a low skew
梅2/4, 梅4/6
clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01
mF
capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
The common enable (EN) is synchronous so that the internal
dividers will only be enabled/disabled when the internal clock is
already in the LOW state. This avoids any chance of generating a runt
clock pulse on the internal clock when the device is enabled/disabled
as can happen with an asynchronous control. An internal runt pulse
could lead to losing synchronization between the internal divider
stages. The internal enable flip-flop is clocked on the falling edge of
the input clock, therefore, all associated specification limits are
referenced to the negative edge of the clock input.
Upon startup, the internal flip-flops will attain a random state;
therefore, for systems which utilize multiple EL39s, the Master Reset
(MR) input must be asserted to ensure synchronization. For systems
which only use one EL39, the MR pin need not be exercised as the
internal divider design ensures synchronization between the
梅2/4
and
the
梅4/6
outputs of a single device.
Features
http://onsemi.com
SO鈭?0 WB
DW SUFFIX
CASE 751D
MARKING DIAGRAM*
20
100EL39
AWLYYWWG
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
50 ps Output-to-Output Skew
Synchronous Enable/Disable
Master Reset for Synchronization
ESD Protection: Human Body Model; > 2 kV,
Machine Model; > 100 V
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: V
CC
= 4.2 V to 5.7 V with V
EE
= 0 V
NECL Mode Operating Range: V
CC
= 0 V with
V
EE
=
鈭?.2
V to
鈭?.7
V
Internal Input Pulldown Resistors on EN, MR, CLK(s), and
DIVSEL(s)
Q Output will Default LOW with Inputs Open or at V
EE
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 V鈭? @ 0.125 in,
Oxygen Index 28 to 34
Transistor Count = 419 devices
Pb鈭扚ree Packages are Available*
1
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb鈭扚ree Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
*For additional information on our Pb鈭扚ree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
漏
Semiconductor Components Industries, LLC, 2006
November, 2006
鈭?/div>
Rev. 6
1
Publication Order Number:
MC100EL39/D
MC100EL39DWG相關(guān)型號PDF文件下載
1
2
3
4
5
6
7
