MC10EL34, MC100EL34
5V ECL
梅2, 梅4, 梅8
Clock
Generation Chip
Description
The MC10/100EL34 is a low skew
梅2, 梅4, 梅8
clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The V
BB
pin, an internally
generated voltage supply, is available to this device only. For
single-ended input conditions, the unused differential input is
connected to V
BB
as a switching reference voltage. V
BB
may also
rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a
0.01
mF
capacitor and limit current sourcing or sinking to 0.5 mA.
When not used, V
BB
should be left open.
The common enable (EN) is synchronous so that the internal
dividers will only be enabled/disabled when the internal clock is
already in the LOW state. This avoids any chance of generating a runt
clock pulse on the internal clock when the device is enabled/disabled
as can happen with an asynchronous control. An internal runt pulse
could lead to losing synchronization between the internal divider
stages. The internal enable flip鈭抐lop is clocked on the falling edge of
the input clock, therefore, all associated specification limits are
referenced to the negative edge of the clock input.
Upon startup, the internal flip-flops will attain a random state; the
master reset (MR) input allows for the synchronization of the internal
dividers, as well as multiple EL34s in a system.
The 100 Series contains temperature compensation.
Features
http://onsemi.com
16
1
SO鈭?6
D SUFFIX
CASE 751B
MARKING DIAGRAMS*
16
10EL34G
AWLYWW
1
A
WL
YY
WW
G
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb鈭扚ree Package
16
100EL34G
AWLYWW
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
50 ps Output-to-Output Skew
Synchronous Enable/Disable
Master Reset for Synchronization
PECL Mode Operating Range:
V
CC
= 4.2 V to 5.7 V with V
EE
= 0 V
鈥?/div>
NECL Mode Operating Range:
V
CC
= 0 V with V
EE
=
鈭?.2
V to
鈭?.7
V
鈥?/div>
Internal Input 75 kW Pulldown Resistors on CLK(s), EN, and MR
鈥?/div>
Pb鈭扚ree Packages are Available*
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
*For additional information on our Pb鈭扚ree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
漏
Semiconductor Components Industries, LLC, 2006
November, 2006
鈭?/div>
Rev. 10
1
Publication Order Number:
MC10EL34/D
1
2
3
4
5
6
7
8
