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MC100E452FNG Datasheet

  • MC100E452FNG

  • ON Semiconductor [5V ECL 5-Bit Differential Register]

  • ONSEMI

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MC10E452, MC100E452
5V ECL 5-Bit Differential
Register
Description
The MC10E/100E452 is a 5-bit differential register with differential
data (inputs and outputs) and clock. The registers are triggered by a
positive transition of the positive clock (CLK) input. A high on the
Master Reset (MR) asynchronously resets all registers so that the Q
outputs go LOW.
The differential input structures are clamped so that the inputs of
unused registers can be left open without upsetting the bias network of
the device. The clamping action will assert the D and the CLK sides of
the inputs. Because of the edge triggered flip-flop nature of the device
simultaneously opening both the clock and data inputs will result in an
output which reaches an unidentified but valid state. Note that the
input clamps only operate when both inputs fall to 2.5 V below V
CC
.
The fully differential design of the device makes it ideal for very
high frequency applications where a registered data path is necessary.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01
mF
capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
The 100 Series contains temperature compensation.
Features
http://onsemi.com
PLCC鈭?8
FN SUFFIX
CASE 776
MARKING DIAGRAM*
1 28
MCxxxE452FNG
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Differential D, CLK and Q; V
BB
Reference Available
1100 MHz Min. Toggle Frequency
Asynchronous Master Reset
PECL Mode Operating Range: V
CC
= 4.2 V to 5.7 V
with V
EE
= 0 V
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
=
鈭?.2
V to
鈭?.7
V
Internal Input 50 kW Pulldown Resistors, Output Q
3
will Default to
Low State When Inputs Are Left Open
ESD Protection: Human Body Model; > 2 kV
Machine Model; > 200 V
Charged Device Model; > 2 kV
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level:
Pb = 1
Pb鈭扚ree = 3
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 V鈭? @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 315 devices
Pb鈭扚ree Packages are Available*
xxx
A
WL
YY
WW
G
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb鈭扚ree Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
*For additional information on our Pb鈭扚ree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
漏
Semiconductor Components Industries, LLC, 2006
November, 2006
鈭?/div>
Rev. 11
1
Publication Order Number:
MC10E452/D

MC100E452FNG PDF文件相關(guān)型號

MC100E452FNR2,MC100E452FNR2G,MC10E452FNG,MC10E452FNR2,MC10E452FNR2G

MC100E452FNG 產(chǎn)品屬性

  • 37

  • 集成電路 (IC)

  • 邏輯 - 鎖銷

  • 100E

  • D 型寄存器

  • 5 x 1:1

  • 差分

  • 4.2 V ~ 5.7 V

  • 1

  • 600ps

  • -

  • 0°C ~ 85°C

  • 表面貼裝

  • 28-LCC（J 形引線）

  • 28-PLCC（11.51x11.51）

  • 管件

  • MC100E452FNGOS

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