MC10E445, MC100E445
5V ECL 4-Bit Serial/Parallel
Converter
Description
The MC10/100E445 is an integrated 4-bit serial to parallel data
converter. The device is designed to operate for NRZ data rates of up to
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2.0 Gb/s. The chip generates a divide by 4 and a divide by 8 clock for
both 4-bit conversion and a two chip 8-bit conversion function. The
conversion sequence was chosen to convert the first serial bit to Q0, the
second to Q1 etc.
PLCC鈭?8
FN SUFFIX
Two selectable serial inputs provide a loopback capability for testing
CASE 776
purposes when the device is used in conjunction with the E446 parallel to
serial converter.
The start bit for conversion can be moved using the SYNC input. A
single pulse applied asynchronously for at least two input clock cycles
MARKING DIAGRAM*
shifts the start bit for conversion from Qn to Qn鈭?. For each additional
1 28
shift required an additional pulse must be applied to the SYNC input.
Asserting the SYNC input will force the internal clock dividers to
鈥渟wallow鈥?a clock pulse, effectively shifting a bit from the Qn to the Qn鈭?
output (see Timing Diagram B).
MCxxxE445FNG
The MODE input is used to select the conversion mode of the device.
AWLYYWW
With the MODE input LOW, or open, the device will function as a 4-bit
converter. When the mode input is driven HIGH the data on the output will
change on every eighth clock cycle thus allowing for an 8-bit conversion
xxx
= 10 or 100
scheme using two E445鈥檚. When cascaded in an 8-bit conversion scheme
A
= Assembly Location
the devices will not operate at the 2.0 Gb/s data rate of a single device.
WL
= Wafer Lot
Refer to the applications section of this data sheet for more information on
YY
= Year
cascading the E445.
WW
= Work Week
Upon power-up the internal flip-flops will attain a random state. To
G
= Pb鈭扚ree Package
synchronize multiple E445鈥檚 in a system the master reset must be asserted.
The V
BB
pin, an internally generated voltage supply, is available to this
*For additional marking information, refer to
device only. For single-ended input conditions, the unused differential
Application Note AND8002/D.
input is connected to V
BB
as a switching reference voltage. V
BB
may also
rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a
ORDERING INFORMATION
0.01
mF
capacitor and limit current sourcing or sinking to 0.5 mA. When
See detailed ordering and shipping information in the package
not used, V
BB
should be left open.
dimensions section on page 11 of this data sheet.
The 100 Series contains temperature compensation.
Features
鈥?/div>
ESD Protection: Human Body Model; > 2 kV,
鈥?/div>
On-Chip Clock
梅4
and
梅8
Machine Model; > 100 V
鈥?/div>
2.0 Gb/s Data Rate Capability
鈥?/div>
Meets or Exceeds JEDEC Spec EIA/JESD78
IC Latchup Test
鈥?/div>
Differential Clock and Serial Inputs
鈥?/div>
Moisture Sensitivity Level: Pb = 1; Pb鈭扚ree = 3
鈥?/div>
V
BB
Output for Single-Ended Input Applications
For Additional Information, see Application Note
鈥?/div>
Asynchronous Data Synchronization
AND8003/D
鈥?/div>
Mode Select to Expand to 8-Bits
鈥?/div>
Flammability Rating: UL 94 V鈭? @ 0.125 in,
鈥?/div>
PECL Mode Operating Range: V
CC
= 4.2 V to 5.7 V
Oxygen Index: 28 to 34
with V
EE
= 0 V
鈥?/div>
Transistor Count = 528 devices
鈥?/div>
NECL Mode Operating Range: V
CC
= 0 V
鈥?/div>
PECL Mode Operating Range: V
CC
= 4.2 V to 5.7 V
with V
EE
=
鈭?.2
V to
鈭?.7
V
with V
EE
= 0 V
鈥?/div>
Internal Input 50 kW Pulldown Resistors
鈥?/div>
Pb鈭扚ree Packages are Available*
*For additional information on our Pb鈭扚ree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
漏
Semiconductor Components Industries, LLC, 2006
November, 2006
鈭?/div>
Rev. 12
1
Publication Order Number:
MC10E445/D
MC100E445FNG PDF文件相關(guān)型號
MC100E445FNR2
MC100E445FNG 產(chǎn)品屬性
37
集成電路 (IC)
接口 - 專用
-
數(shù)據(jù)管理
差分
4.2 V ~ 5.7 V
28-LCC（J 形引線）
28-PLCC（11.51x11.51）
管件
表面貼裝
MC100E445FNG相關(guān)型號PDF文件下載
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