MC100E310
5V ECL Low Voltage 2:8
Differential Fanout Buffer
Description
The MC100E310 is a low voltage, low skew 2:8 differential ECL
fanout buffer designed with clock distribution in mind. The device
features fully differential clock paths to minimize both device and
system skew. The E310 offers two selectable clock inputs to allow for
redundant or test clocks to be incorporated into the system clock trees.
The lowest TPD delay time results from terminating only one output
pair, and the greatest TPD delay time results from terminating all the
output pairs. This shift is about 10鈭?0 pS in TPD. The skew between
any two output pairs within a device is typically about 25 nS. If other
output pairs are not terminated, the lowest TPD delay time results
from both output pairs and the skew is typically 25 nS. When all
outputs are terminated, the greatest TPD (delay time) occurs and all
outputs display about the same 10
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20 ps increase in TPD, so the
relative skew between any two output pairs remains about 25 ns.
For more information on using PECL, designers should refer to
ON Semiconductor Application Note AN1406/D.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01
mF
capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
The 100 Series Contains Temperature Compensation
Features
http://onsemi.com
PLCC鈭?8
FN SUFFIX
CASE 776
MARKING DIAGRAM*
1 28
MC100E310FNG
AWLYYWW
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb鈭扚ree Package
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Dual Differential Fanout Buffers
200 ps Part鈭抰o鈭扨art Skew
50 ps Output鈭抰o鈭扥utput Skew
28鈭抣ead PLCC Packaging
Q Output will Default LOW with Inputs Open or at V
EE
PECL Mode Operating Range: V
CC
= 4.2 V to 5.7 V
with V
EE
= 0 V
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
=
鈭?.2
V to
鈭?.7
V
Internal Input 50 kW Pulldown Resistors
ESD Protection: Human Body Model; >2 kV,
Machine Model; >200 V
Meets or Exceeds JEDEC Spec EIA/JESD78 IC
Latchup Test
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
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Moisture Sensitivity Level: Pb = 1; Pb鈭扚ree = 3
For Additional Information, see Application Note
AND8003/D
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Flammability Rating: UL 94 V鈭? @ 0.125 in,
Oxygen Index: 28 to 34
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Transistor Count = 212 devices
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Pb鈭扚ree Packages are Available*
*For additional information on our Pb鈭扚ree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
漏
Semiconductor Components Industries, LLC, 2006
October, 2006
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Rev. 5
1
Publication Order Number:
MC100E310/D
MC100E310FNG PDF文件相關(guān)型號(hào)
MC100E310FNR2G
MC100E310FNG相關(guān)型號(hào)PDF文件下載
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