MC10E196, MC100E196
5V ECL Programmable
Delay Chip
Description
The MC10E/100E196 is a programmable delay chip (PDC)
designed primarily for very accurate differential ECL input edge
placement applications.
The delay section consists of a chain of gates and a linear ramp delay
adjust organized as shown in the logic symbol. The first two delay
elements feature gates that have been modified to have delays
1.25 and 1.5 times the basic gate delay of approximately 80 ps. These
two elements provide the E196 with a digitally-selectable resolution
of approximately 20 ps. The required device delay is selected by the
seven address inputs D[0:6], which are latched on chip by a high signal
on the latch enable (LEN) control.
The FTUNE input takes an analog voltage and applies it to an
internal linear ramp for reducing the 20 ps Least Significant Bit (LSB)
minimum resolution still further. The FTUNE input is what
differentiates the E196 from the E195.
An eighth latched input, D7, is provided for cascading multiple
PDC鈥檚 for increased programmable range. The cascade logic allows
full control of multiple PDC鈥檚, at the expense of only a single added
line to the data bus for each additional PDC, without the need for any
external gating.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01
mF
capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
The 100 Series contains temperature compensation.
Features
http://onsemi.com
PLCC鈭?8
FN SUFFIX
CASE 776
MARKING DIAGRAM*
1
MCxxxE196FNG
AWLYYWW
xxx
A
WL
YY
WW
G
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb鈭扚ree Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
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2.0 ns Worst Case Delay Range
鈮?0
ps/Delay Step Resolution
Linear Input for Tighter Resolution
>1.0 GHz Bandwidth
On Chip Cascade Circuitry
PECL Mode Operating Range: V
CC
= 4.2 V to 5.7 V
with V
EE
= 0 V
鈥?/div>
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
=
鈭?.2
V to
鈭?.7
V
鈥?/div>
Internal Input 50 kW Pulldown Resistors
鈥?/div>
ESD Protection: Human Body Model; > 1 kV,
Machine Model; > 75 V
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Meets or Exceeds JEDEC Spec EIA/JESD78 IC
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Latchup Test
Moisture Sensitivity Level: Pb = 1; Pb鈭扚ree = 3
For Additional Information, see Application Note
AND8003/D
Flammability Rating: UL 94 V鈭? @ 1.125 in,
Oxygen Index: 28 to 34
Transistor Count = 425 devices
Pb鈭扚ree Packages are Available*
*For additional information on our Pb鈭扚ree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
漏
Semiconductor Components Industries, LLC, 2006
November, 2006
鈭?/div>
Rev. 9
1
Publication Order Number:
MC10E196/D
MC100E196FNR2 PDF文件相關(guān)型號
MC100E196FNR2G,MC10E196_06,MC10E196FNR2
MC100E196FNR2 產(chǎn)品屬性
500
集成電路 (IC)
時鐘/計時 - 延遲線
100E
128
可編程
1.39ns
20ps
1.39ns ~ 3.63ns
1
4.2 V ~ 5.7 V
0°C ~ 85°C
表面貼裝
28-LCC（J 形引線）
28-PLCC（11.51x11.51）
帶卷 (TR)
MC100E196FNR2相關(guān)型號PDF文件下載
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