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MC100E155FNR2 Datasheet

  • MC100E155FNR2

  • ON Semiconductor [5V ECL 6−Bit 2:1 Mux−...

  • ONSEMI

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MC10E155, MC100E155
5V ECL 6鈭払it 2:1
Mux鈭扡atch
Description
The MC10E/100E155 contains six 2:1 multiplexers followed by
transparent latches with single鈭抏nded outputs. When both Latch
Enables (LEN1, LEN2) are LOW, the latch is transparent, and output
data is controlled by the multiplexer select control, SEL. A logic
HIGH on either LEN1 or LEN2 (or both) latches the outputs. The
Master Reset (MR) overrides all other controls to set the Q outputs
LOW.
The 100 Series contains temperature compensation.
Features
http://onsemi.com
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850 ps Max. LEN to Output
825 ps Max. D to Output
Single鈭扙nded Outputs
Asynchronous Master Reset
Dual Latch鈭扙nables
PECL Mode Operating Range: V
CC
= 4.2 V to 5.7 V
with V
EE
= 0 V
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
=
鈭?.2
V to
鈭?.7
V
Internal Input 50 kW Pulldown Resistors
ESD Protection: Human Body Model; > 2 kV,
Machine Model; > 200 V
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level:
Pb = 1
Pb鈭扚ree = 3
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 V鈭? @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 239 Devices
Pb鈭扚ree Packages are Available*
PLCC鈭?8
FN SUFFIX
CASE 776
MARKING DIAGRAM*
1
MCxxxE155FNG
AWLYYWW
xxx
A
WL
YY
WW
G
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb鈭扚ree Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
*For additional information on our Pb鈭扚ree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
漏
Semiconductor Components Industries, LLC, 2006
November, 2006
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Rev. 8
1
Publication Order Number:
MC10E155/D

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