MC10E136, MC100E136
5V ECL 6-Bit Universal
Up/Down Counter
Description
The MC10E/100E136 is a 6-bit synchronous, presettable,
cascadable universal counter. The device generates a look-ahead-carry
output and accepts a look-ahead-carry input. These two features allow
for the cascading of multiple E136鈥檚 for wider bit width counters that
operate at very nearly the same frequency as the stand alone counter.
The CLOUT output will pulse LOW for one clock cycle one count
before the E136 reaches terminal count. The COUT output will pulse
LOW for one clock cycle when the counter reaches terminal count.
For more information on utilizing the look-ahead-carry features of the
device please refer to the applications section of this data sheet. The
differential COUT output facilitates the E136鈥檚 use in programmable
divider and self-stopping counter applications.
Unlike the H136 and other similar universal counter designs, the E136
carry鈭抩ut and look-ahead-carry鈭抩ut signals are registered on chip.
This design alleviates the glitch problem seen on many counters
where the carry out signals are merely gated. Because of this
architecture there are some minor functional differences between the
E136 and H136 counters. The user, regardless of familiarity with the
H136, should read this data sheet carefully. Note specifically (see
logic diagram) the operation of the carry out outputs and the
look-ahead-carry in input when utilizing the master reset.
When left open all of the input pins will be pulled LOW via an input
pull鈭抎own resistor. The master reset is an asynchronous signal which
when asserted will force the Q outputs LOW.
The Q outputs need not be terminated for the E136 to function
properly, in fact if these outputs will not be used in a system it is
recommended to save power and minimize noise that they be left
open. This practice will minimize switching noise which can reduce
the maximum count frequency of the device or significantly reduce
margins against other noise in the system.
The 100 Series contains temperature compensation.
Features
http://onsemi.com
PLCC鈭?8
FN SUFFIX
CASE 776
MARKING DIAGRAM*
1
MCxxxE136G
AWLYYWW
xxx
A
WL
YY
WW
G
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb鈭扚ree Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
550 MHz Count Frequency
Fully Synchronous Up and Down Counting
Look-Ahead-Carry Input and Output
Asynchronous Master Reset
PECL Mode Operating Range: V
CC
= 4.2 V to 5.7 V
with V
EE
= 0 V
鈥?/div>
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
=
鈭?.2
V to
鈭?.7
V
鈥?/div>
Internal Input 50 kW Pulldown Resistors
鈥?/div>
ESD Protection: Human Body Model: > 2 kV,
Machine Model: > 200 V
鈥?/div>
Meets or Exceeds JEDEC Standard EIA/JESD78
鈥?/div>
鈥?/div>
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鈥?/div>
IC Latchup Test
Moisture Sensitivity Level: Pb = 1; Pb鈭扚ree = 3
For Additional Information, see Application Note
AND8003/D
Flammability Rating: UL 94 V鈭? @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 506 devices
Pb鈭扚ree Packages are Available*
*For additional information on our Pb鈭扚ree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
漏
Semiconductor Components Industries, LLC, 2006
November, 2006
鈭?/div>
Rev. 9
1
Publication Order Number:
MC10E136/D
MC100E136FNG PDF文件相關(guān)型號(hào)
MC100E136FNR2,MC100E136FNR2G,MC10E136FNG,MC10E136FNR2,MC10E136FNR2G
MC100E136FNG 產(chǎn)品屬性
37
集成電路 (IC)
邏輯 -計(jì)數(shù)器，除法器
100E
二進(jìn)制計(jì)數(shù)器
上，下
1
6
異步
同步
650MHz
正邊沿
4.2 V ~ 5.7 V
0°C ~ 85°C
表面貼裝
28-LCC（J 形引線）
28-PLCC（11.51x11.51）
管件
MC100E136FNG相關(guān)型號(hào)PDF文件下載
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