19-2390; Rev 0; 4/02
Lowest Jitter Quad PECL-to-ECL
Differential Translators
General Description
The MAX9424鈥揗AX9427 high-speed, low-skew quad
PECL-to-ECL translators are designed for high-speed
data and clock driver applications. These devices feature
an ultra-low 0.24ps
(RMS)
random jitter and channel-to-
channel skew is less than 90ps in asynchronous mode.
The four channels can be operated synchronously with
an external clock, or in asynchronous mode determined
by the state of the SEL input. An enable input provides
the ability to force all the outputs to a differential low state.
The parts differ from one another by their input and out-
put termination options. The input options are an open
input or an internal differential 100鈩?termination. The
output options are an open-emitter output or a series
50鈩?termination. See
Ordering Information.
The MAX9424鈥揗AX9427 operate from a positive voltage
supply of +2.375V to +5.5V, and a negative supply volt-
age of -2.375V to -5.5V and operate across the extended
temperature range of -40擄C to +85擄C. They are offered in
32-pin 5mm x 5mm TQFP and space-saving 5mm x 5mm
QFN packages.
o
0.24ps RMS Added Random Jitter
o
10ps Channel-to-Channel Skew in Synchronous
Mode
o
Guaranteed 500mV Differential Output at 3GHz
Clock Frequency
o
420ps Propagation Delay in Asynchronous Mode
o
Functionally Compatible with
SK4426 (MAX9424)
SK4430 (MAX9425)
SK4436 (MAX9426)
SK4440 (MAX9427)
o
Integrated 50鈩?Outputs (MAX9425/MAX9427)
o
Integrated 100鈩?Inputs (MAX9426/MAX9427)
o
Synchronous/Asynchronous Operation
Features
MAX9424鈥揗AX9427
Ordering Information
INPUT OUTPUT
PART
(IN_, (OUT_,
OUT_)
IN_)
MAX9424EHJ
-40擄C to +85擄C 32 TQFP
Open
Open
MAX9424EGJ* -40擄C to +85擄C 32 QFN
Open
Open
MAX9425EHJ
-40擄C to +85擄C 32 TQFP
Open
50鈩?/div>
MAX9425EGJ* -40擄C to +85擄C 32 QFN
Open
50鈩?/div>
MAX9426EHJ
-40擄C to +85擄C 32 TQFP
100鈩?/div>
Open
MAX9426EGJ* -40擄C to +85擄C 32 QFN
100鈩?/div>
Open
MAX9427EHJ
-40擄C to +85擄C 32 TQFP
100鈩?/div>
50鈩?/div>
MAX9427EGJ* -40擄C to +85擄C 32 QFN
100鈩?/div>
50鈩?/div>
*Future
product鈥攃ontact factory for availability.
TEMP
RANGE
PIN-
PACKAGE
Applications
Data and Clock Driver and Buffer
Central Office Backplane Clock Distribution
DSLAM Backplane
Base Station
ATE
Pin Configurations
OUT0
OUT0
V
GG
TOP VIEW
OUT0
OUT0
V
GG
V
EE
IN0
IN0
IN1
IN1
TOP VIEW
IN0
IN0
32
31
V
EE
IN1
30
29
28
27
32
V
CC
SEL
SEL
CLK
CLK
EN
EN
V
CC
1
2
3
4
5
6
7
8
9
IN3
31
30
29
28
27
26
25
24 V
GG
23 OUT1
22 OUT1
*
26
25
*
IN1
V
CC
SEL
SEL
CLK
CLK
EN
EN
V
CC
1
2
3
4
5
6
7
8
10
11
12
13
14
15
16
*
*
24
23
22
V
GG
OUT1
OUT1
V
EE
V
EE
OUT2
OUT2
V
GG
MAX9424
MAX9425
MAX9426
MAX9427
21 V
EE
20 V
EE
19 OUT2
18 OUT2
17 V
GG
MAX9424
MAX9425
MAX9426
MAX9427
21
20
19
18
17
10
IN3
11
V
GG
12
OUT3
13
OUT3
14
V
EE
15
IN2
16
9
OUT3
OUT3
V
EE
IN2
IN3
IN3
IN2
V
GG
TQFP (5mm x 5mm)
QFN
NOTE:
CORNER PINS ARE CONNECTED TO V
GG
.
________________________________________________________________
Maxim Integrated Products
IN2
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim鈥檚 website at www.maxim-ic.com.
MAX9425 PDF文件相關(guān)型號
MAX9426,MAX9427
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