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MAX9325 Datasheet

  • MAX9325

  • 2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver

  • Maxim   Maxim

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19-2511; Rev 1; 7/02
2:8 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
General Description
The MAX9325 low-skew, 2:8 differential driver features
extremely low output-to-output skew (50ps max) and
part-to-part skew (225ps max). These features make
the device ideal for clock and data distribution across a
backplane or board. The device selects one of the two
differential HSTL or LVECL/LVPECL inputs and repeats
them at eight differential outputs. Outputs are compati-
ble with LVECL and LVPECL, and can directly drive
50鈩?terminated transmission lines.
The differential inputs can be configured to accept a
single-ended signal when the unused complementary
input is connected to the on-chip reference output volt-
age V
BB.
All inputs have internal pulldown resistors to
V
EE.
The internal pulldowns and a fail-safe circuit
ensure differential low default outputs when the inputs
are left open or at V
EE
.
The MAX9325 operates over a 2.375V to 3.8V supply
range for interfacing to differential HSTL and LVPECL
signals. This allows high-performance clock or data dis-
tribution in systems with a nominal +2.5V or +3.3V sup-
ply. For LVECL operation, the device operates with a
-2.375V to -3.8V supply.
The MAX9325 is offered in 28-lead PLCC and space-
saving 28-lead QFN packages. The MAX9325 is speci-
fied for operation from -40擄C to +85擄C.
o
50ps (max) Output-to-Output Skew
o
1.5ps
RMS
(max) Random Jitter
o
Guaranteed 300mV Differential Output at 700MHz
o
+2.375V to +3.8V Supplies for Differential
HSTL/LVPECL
o
-2.375V to -3.8V Supplies for Differential LVECL
o
Two Selectable Differential Inputs
o
On-Chip Reference for Single-Ended Inputs
o
Outputs Low for Inputs Open or at V
EE
o
Pin Compatible with MC100LVE310
Features
MAX9325
Ordering Information
PART
MAX9325EQI
MAX9325ETI*
TEMP RANGE
-40擄C to +85擄C
-40擄C to +85擄C
PIN-PACKAGE
28 PLCC
28 QFN 5mm x 5mm
*Future
product鈥攃ontact factory for availability.
Functional Diagram appears at end of data sheet.
Applications
Precision Clock Distribution
Low-Jitter Data Repeaters
Pin Configurations
V
CC
Q0
Q0
Q1
Q1
Q2
Q2
V
CC
TOP VIEW
Q0
Q0
Q1
Q1
Q2
Q2
INPUT SELECT TRUTH TABLE
CLK_SEL
INPUT CLOCK
CLK0, CLK0 SELECTED
CLK1, CLK1 SELECTED
28
27
26
25
24
23
22
25 24
23 22 21
20
19
*
*
L
V
EE
CLK_SEL
CLKO
V
CC
CLKO
V
BB
CLK1
26
27
28
1
2
3
4
18
17
16
Q3
Q3
Q4
V
CC
Q4
Q5
Q5
V
EE
CLK_SEL
CLKO
V
CC
CLKO
V
BB
CLK1
1
2
3
4
5
6
7
*
21
20
19
Q3
Q3
Q4
V
CC
Q4
Q5
Q5
H
MAX9325
15
14
13
12
MAX9325
18
17
16
15
*
5
6
7
Q7
8
9
10
Q6
11
Q6
CLK1
N.C.
V
CC
Q7
10
11
12
13
Q6
CLK1
Q7
N.C.
QFN
*CORNER PINS AND EXPOSED PAD ARE CONNECTED TO V
EE
.
________________________________________________________________
Maxim Integrated Products
V
CC
Q7
Q6
PLCC
14
8
9
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim鈥檚 website at www.maxim-ic.com.

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