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MAX9324 Datasheet

  • MAX9324

  • One-to-Five LVPECL/LVCMOS Output Clock and Data Driver

  • Maxim   Maxim

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19-2576; Rev 0; 10/02
One-to-Five LVPECL/LVCMOS Output Clock and
Data Driver
General Description
The MAX9324 low-skew, low-jitter, clock and data driver
distributes a differential LVPECL input to four differential
LVPECL outputs and one single-ended LVCMOS output.
All outputs default to logic low when the differential inputs
equal GND or are left open. The MAX9324 operates from
3.0V to 3.6V, making it ideal for 3.3V systems, and con-
sumes only 25mA (max) of supply current.
The MAX9324 features low 150ps (max) part-to-part
skew, low 15ps output-to-output skew, and low 1.7ps
RMS jitter, making the device ideal for clock and data
distribution across a backplane or board. CLK_EN and
SEOUT_Z control the status of the various outputs.
Asserting CLK_EN low configures the differential (Q_,
Q_)
outputs to a differential low condition and SEOUT to
a single-ended logic-low state. CLK_EN operation is
synchronous with the CLK_ inputs. A logic high on
SEOUT_Z places SEOUT in a high-impedance state.
SEOUT_Z is asynchronous with the CLK (CLK) inputs.
The MAX9324 is available in space-saving 20-pin
TSSOP and ultra-small 20-pin 4mm
鉁?/div>
4mm thin QFN
packages and operates over the extended (-40擄C to
+85擄C) temperature range.
o
1.7ps
RMS
Added Random Jitter
o
150ps (max) Part-to-Part Skew
o
450ps Propagation Delay
o
Synchronous Output Enable/Disable
o
Single-Ended Monitor Output
o
Outputs Assert Low when CLK,
CLK
are Open or
at GND
o
3.0V to 3.6V Supply Voltage Range
o
-40擄C to +85擄C Operating Temperature Range
Features
o
15ps Differential Output-to-Output Skew
MAX9324
Ordering Information
PART
MAX9324EUP
MAX9324ETP*
TEMP RANGE
-40擄C to +85擄C
-40擄C to +85擄C
PIN-PACKAGE
20 TSSOP
20 Thin QFN-EP**
Applications
Precision Clock Distribution
Low-Jitter Data Repeater
Data and Clock Driver and Buffer
Central-Office Backplane Clock Distribution
DSLAM Backplane
Base Station
ATE
CLK_EN
*Future
product鈥擟ontact factory for availability.
**EP
= Exposed paddle.
Functional Diagram and Typical Operating Circuit appear at
end of data sheet.
Pin Configurations
GND
N.C.
Q0
17
TOP VIEW
20
19
18
16
GND 1
20 Q0
19 Q0
18 V
CC
17 Q1
CLK_EN 2
N.C. 3
SEOUT 4
GND 5
12 Q2
11 Q2
N.C. 6
SEOUT_Z 7
CLK 8
Q0
SEOUT 1
GND 2
N.C. 3
SEOUT_Z 4
CLK 5
15 V
CC
14 Q1
MAX9324
**EXPOSED PADDLE
13 Q1
MAX9324
16 Q1
15 Q2
14 Q2
13 V
CC
12 Q3
11 Q3
6
CLK
7
V
CC
8
Q3
9
Q3
10
V
CC
CLK 9
V
CC
10
THIN QFN-EP** (4mm x 4mm)
**CONNECT EXPOSED PADDLE TO GND.
TSSOP
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim鈥檚 website at www.maxim-ic.com.

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