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MAX9160 Datasheet

  • MAX9160

  • LVDS or LVTTL/LVCMOS Input to 14 LVTTL/LVCMOS Output Clock D...

  • Maxim   Maxim

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19-2392; Rev 0; 4/02
LVDS or LVTTL/LVCMOS Input to
14 LVTTL/LVCMOS Output Clock Driver
General Description
The MAX9160 125MHz, 14-port LVTTL/LVCMOS clock
driver repeats the selected LVDS or LVTTL/LVCMOS
input on two output banks. Each bank consists of seven
LVTTL/LVCMOS series terminated outputs and a bank
enable. The LVDS input has a fail-safe function. The
MAX9160 has a propagation delay that can be adjusted
using an external resistor to set the bias current for an
internal delay cell. The LVTTL/LVCMOS outputs feature
200ps maximum output-to-output skew and
鹵100ps
maxi-
mum added peak-to-peak jitter.
The MAX9160 is designed to operate with a 3.3V sup-
ply voltage over the extended temperature range of
-40擄C to +85擄C. This device is available in 28-pin
exposed- and nonexposed-pad TSSOP and 32-lead
5mm x 5mm QFN packages.
Features
o
LVDS or LVTTL/LVCMOS Input Selection
o
LVDS Input Fail-Safe Sets Outputs High for Open,
Undriven Short, or Undriven Parallel Termination
o
Two Output Banks with Separate Bank Enables
o
Integrated Output Series Termination for 60鈩?/div>
Lines
o
200ps (max) Output-to-Output Skew
o
鹵100ps
(max) Peak-to-Peak Added Output Jitter
o
42% to 58% Output Duty Cycle at 125MHz
o
Guaranteed 125MHz Operating Frequency
o
LVDS Input Is High Impedance with V
CC
= 0V
or Open (Hot Swappable)
o
28-Pin Exposed- and Nonexposed-Pad TSSOP
or 32-Lead QFN Packages
o
-40擄C to +85擄C Operating Temperature
o
3.0V to 3.6V Supply Voltage
MAX9160
Applications
Cellular Base Stations
Servers
Add/Drop Multiplexers
Digital Cross-Connects
DSLAMs
Networking Equipment
Ordering Information
Typical Application Circuit and Functional Diagram appear
at end of data sheet.
PART
MAX9160EUI
MAX9160AEUI
MAX9160EGJ*
TEMP RANGE
-40擄C to +85擄C
-40擄C to +85擄C
-40擄C to +85擄C
PIN-PACKAGE
28 TSSOP
28 TSSOP-EP**
32 QFN-EP
Pin Configurations
TOP VIEW
OUTA5 1
OUTA6 2
ENA 3
SEL 4
SE_IN 5
V
CC
6
GND 7
IN+ 8
IN- 9
GND 10
RSET 11
ENB 12
OUTB0 13
OUTB1 14
28 OUTA4
27 OUTA3
26 GND
25 OUTA2
24 OUTA1
*Future
product鈥攃ontact factory for availability.
**Exposed
pad.
Function Table
EN_
H
H
H
H
SEL
H
H
L or
open
L or
open
L or
open
X
SE_IN
H
L or
open
X
X
V
ID
X
X
鈮?/div>
+50mV
鈮?/div>
-50mV
Open, undriven short, or
undriven parallel termination
X
OUT_
H
L
H
L
MAX9160
23 V
CC
22 OUTA0
21 OUTB6
20 GND
19 OUTB5
18 OUTB4
17 V
CC
16 OUTB3
15 OUTB2
H
L or
Open
X
H
X
L
TSSOP
Pin Configurations continued at end of data sheet.
V
ID
= V
IN+
- V
IN-
H = high logic level
L = low logic level
X = don鈥檛 care
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim鈥檚 website at www.maxim-ic.com.

MAX9160 PDF文件相關型號

MAX9160AEUI

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