19-1212; Rev 0; 3/97
MAX3680 Evaluation Kit
_______________General Description
The MAX3680 evaluation kit (EV kit) simplifies evalua-
tion of the MAX3680 622Mbps, SDH/SONET 1:8 deseri-
alizer. The EV kit requires only a +3.3V supply, and
includes all the external components necessary to inter-
face with 3.3V PECL/TTL logic. The board can be con-
nected directly to the output of a clock-and-data-recov-
ery circuit (such as the MAX3675) and to the TTL input
of an overhead termination circuit. It can also be used
with a signal generator and an oscilloscope to evaluate
the MAX3680鈥檚 basic functionality.
____________________________Features
o
Single +3.3V Supply
o
Inputs Terminated for Interfacing with 3.3V PECL
o
Outputs Configured for 50鈩?or High-Impedance
Interface
o
Fully Assembled and Tested
Evaluates: MAX3680
______________Ordering Information
PART
MAX3680EVKIT-SO
TEMP. RANGE
-40擄C to +85擄C
BOARD TYPE
Surface Mount
____________________Component List
DESIGNATION QTY
C1鈥揅4
C5
4
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DESCRIPTION
0.1碌F ceramic capacitors
33碌F, 10V tantalum capacitor
AVX TAJC336K010 or
Sprague 293D336X0010C2
2.2碌F tantalum capacitor
AVX TAJA225K010 or
Sprague 293D225X0010A2
100pF ceramic capacitors
SMA connectors (PC edge mount)
56nH inductor
Coilcraft 0805CS-560-XKBC
82鈩? 5% resistors
130鈩? 5% resistors
2.4k鈩? 5% resistors
2-pin headers
MAX3680EAI
MAX3680 data sheet
_______________Detailed Description
The MAX3680 EV kit simplifies evaluation of the
MAX3680 622Mbps, SDH/SONET 1:8 deserializer. The
EV kit operates from a single +3.3V supply and
includes all the external components necessary to inter-
face with 3.3V PECL/TTL logic.
Each PECL input (SCLK+, SCLK-, SD+, SD-) is termi-
nated on the EV board with the Thevenin equivalent of
50鈩?to (V
CC
- 2V). These inputs can be driven directly
by any 3.3V PECL device's output, such as a clock-
and-data-recovery circuit (e.g., the MAX3675). The syn-
chronization input (SYNC) is a TTL input.
The TTL outputs (PCLK, PD_) can interface to either
50鈩?or high-impedance inputs. To interface to 50鈩?/div>
inputs, connect the inputs directly to the SMA connec-
tors labeled PCLK and PD0鈥揚(yáng)D7. This configuration
forms a 50-to-1 voltage divider that maintains a high-
impedance load to each TTL output while interfacing to
50鈩? To interface to high-impedance inputs, connect
the inputs to the 2-pin headers at R9鈥揜17, which pro-
vide direct connections to the TTL outputs.
C6
C7鈥揅12
J3鈥揓16
L1
R1, R3, R5, R7
R2, R4, R6, R8
R9鈥揜17
+3.3V, GND
JR9鈥揓R17
U1
None
1
6
14
1
4
4
9
11
1
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______________Component Suppliers
SUPPLIER
AVX
Coilcraft
Sprague
PHONE
(803) 946-0690
(847) 639-6400
(603) 224-1961
FAX
(803) 626-3123
(847) 639-1469
(603) 224-1430
_____________Layout Considerations
To minimize propagation-delay skew, all PECL input
signal lines are 50鈩?transmission lines of equal length.
To allow accurate characterization of the parallel-clock
to data-output delay, the output data lines (prior to the
series 2.4k鈩?termination resistors) are matched and
kept as short as possible. Excluding the series termina-
tion resistor, each output data line measures approxi-
mately 3pF at the 2-pin header (JR9鈥揓R17).
Please indicate that you are using the MAX3680 when contact-
ing the above component suppliers.
________________________________________________________________
Maxim Integrated Products
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For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
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