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M74HCT125 Datasheet

  • M74HCT125

  • QUAD BUS BUFFERS (3-STATE)

  • STMicroelectronics   STMicroelectronics

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M54/74HCT125
M54/74HCT126
QUAD BUS BUFFERS (3-STATE)
.
.
.
.
.
.
.
HIGH SPEED
t
PD
= 12 ns (TYP.) AT V
CC
= 5 V
LOW POWER DISSIPATION
I
CC
= 4
碌A(chǔ)
(MAX.) AT 25
擄C
OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS
BALANCED PROPAGATION DELAYS
t
PLH
= t
PHL
SYMMETRICAL OUTPUT IMPEDANCE
I
OL
=
錚
OH
錚?/div>
= 6 mA (MIN.)
COMPATIBLE WITH TTL OUTPUTS
V
IH
= 2V (MIN.) V
IL
= 0.8V (MAX)
PIN AND FUNCTION COMPATIBLE
WITH 54/74LS125/126
B1R
(Plastic Package)
F1R
(Ceramic Package)
M1R
(Micro Package)
C1R
(Chip Carrier)
DESCRIPTION
The M54/74HCT125/126 are high speed CMOS
QUAD BUS BUFFER (3-STATE) FABRICATED IN
SILICON GATE C
2
MOS technology. They have the
same high speed performance of LSTTL combined
with true CMOS low power consumption. These de-
vices require the same 3-STATE control input G to
be taken high to make the output go into the high im-
pedance state.This integrated circuit has input and
output characteristics that are fully compatible with
54/74 LSTTL logic families. M54/74HCT devices
are designed to directly interface HSC
2
MOS sys-
tems with TTL and NMOS components. They are
also plug in replacements for LSTTL devices giving
a reduction of power consumption. All inputs are
equipped with protection circuits against static dis-
charge and transient excess voltage.
INPUT AND OUTPUT EQUIVALENT CIRCUIT
ORDER CODES :
M54HCTXXXF1R
M74HCTXXXM1R
M74HCTXXXB1R
M74HCTXXXC1R
PIN CONNECTIONS
(top view)
HCT125
HCT126
NC =
No Internal
Connection
October 1993
1/10

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