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M74HC573 Datasheet

  • M74HC573

  • OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT (NON INVERTING)

  • STMicroelectronics   STMicroelectronics

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M54/74HC563
M54/74HC573
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT
HC563 INVERTING - HC573 NON INVERTING
.
.
.
.
.
.
.
.
HIGH SPEED
t
PD
= 13 ns (TYP.) AT V
CC
= 5 V
LOW POWER DISSIPATION
I
CC
= 4
碌A
(MAX.) AT T
A
= 25
擄C
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS
SYMMETRICAL OUTPUT IMPEDANCE
I
OL
=
錚
OH
錚?
6 mA (MIN.)
BALANCED PROPAGATION DELAYS
t
PLH
= t
PHL
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO 6 V
PIN AND FUNCTION COMPATIBLE
WITH 54/74LS563/573
B1R
(Plastic Package)
F1R
(Ceramic Package)
M1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M54HCXXXF1R
M74HCXXXM1R
M74HCXXXB1R
M74HCXXXC1R
DESCRIPTION
The M54/74HC563 and M54HC573 are high speed
CMOS OCTAL LATCH WITH 3-STATE OUTPUTS
2
fabricated with in silicon gate C MOS technology.
These ICs archive the high speed operation similar
to equivalent LSTTL while maintaning the CMOS
low power dissipation.
These 8 bit D-Type latches are controlled by a latch
enable input (LE) and a output enable input (OE).
While the LE input is held at a high level, the Q
outputs will follow the data input precisely or
inversely. When the LE is taken low, the Q outputs
will be latched precisely or inversely at the logic level
PIN CONNECTION
(top view)
HC563
HC573
of D input data. While the OE input is at low level,
the eight outputs will be in a normal logic state (high
or low logic level) and while high level the outpts will
be in a high impedance state.
The application designer has a choise of
combination of inverting and non inverting outputs.
The three state output configuration and the wide
choise of outline make bus organized system
simple.
All inputs are equipped with protection circuits
against discharge and transient excess voltage.
HC563
HC573
October 1993
1/13

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