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M74HC237B1R Datasheet

  • M74HC237B1R

  • IC, 3 TO 8 LINE DECODER, DIP-16; Logic Type:Line Decoder; No...

  • 259.60KB

  • 11頁

  • STMicroelectronics   STMicroelectronics

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M54HC237
M74HC237
3 TO 8 LINE DECODER LATCH
.
.
.
.
.
.
.
.
HIGH SPEED
t
PD
= 12 ns (TYP.) at V
CC
= 5 V
LOW POWER DISSIPATION
I
CC
= 4
碌A(chǔ)
(MAX.) AT T
A
= 25
擄C
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
SYMMETRICAL OUTPUT IMPEDANCE
錚
OH
錚?/div>
= I
OL
= 4 mA (MIN.)
BALANCED PROPAGATION DELAYS
t
PLH
= t
PHL
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO 6 V
PIN AND FUNCTION COMPATIBLE
WITH 54/74LS237
B1R
(Plastic Package)
F1R
(Ceramic Package)
M1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M54HC237F1R
M74HC237M1R
M74HC237B1R
M74HC237C1R
PIN CONNECTIONS
(top view)
DESCRIPTION
The M54/74HC237 is a high speed CMOS 3 TO 8
LINE DECODER LATCH fabricated in silicon gate
C
2
MOS technology.
It has the same high speed performance of LSTTL
combined with true CMOS low power consumption.
When GL goes from low to high, the address present
at the select inputs (A, B, C) is stored in the latches.
As long as GL remains high no address changes will
be recognized. Output enable controls, G1 and G2
control the state of the outputs independantly of the
select or latch-enable inputs. All of the outputs are low
unless G1 is high and G2 is low. The 鈥橦C237 is ideally
suited for the implementation of glitch-free decoders
in stored-address applications in bus oriented sys-
tems. All inputs are equipped with protection circuits
against static discharge and transient excess voltage.
October 1992
NC =
No Internal
Connection
1/11

M74HC237B1R 產(chǎn)品屬性

  • 25

  • 集成電路 (IC)

  • 邏輯 - 信號開關(guān)，多路復(fù)用器，解碼器

  • 74HC

  • 解碼器

  • 1 x 3:8

  • 1

  • 5.2mA，5.2mA

  • 單電源

  • 2 V ~ 6 V

  • -55°C ~ 125°C

  • 通孔

  • 16-DIP（0.300"，7.62mm）

  • 16-DIP

  • 管件

  • 497-7359-5M74HC237B1R-ND

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