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M34S32
PRELIMINARY DATA
32K Serial I
2
C Bus EEPROM
With User-Defined Read-Only Block and 32-Byte OTP Page
s
TWO WIRE I
2
C SERIAL INTERFACE,
SUPPORTS 400kHz PROTOCOL
COMPATIBLE WITH I
2
C EXTENDED
ADDRESSING
1 MILLION ERASE/WRITE CYCLES
40 YEARS DATA RETENTION
SINGLE SUPPLY VOLTAGE
HARDWARE WRITE CONTROL
USER-DEFINED READ-ONLY BLOCK
32 BYTES OTP PAGE
BYTE and PAGE WRITE (up to 32 BYTES)
BYTE, RANDOM and SEQUENTIAL READ
MODES
SELF TIMED PROGRAMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD and LATCH-UP
PERFORMANCES
Figure 1. Delivery Forms
s
s
s
s
s
s
s
s
s
8
8
1
1
PSDIP8 (BN)
0.25 mm Frame
S08 (MN)
150 mil Width
s
s
s
Figure 2. Logic Diagram
DESCRIPTION
The M34S32 is a 32K bit electrically erasable pro-
grammable memory (EEPROM), organized as
4096 x 8 bits.
Table 1. Signal Names
SDA
SCL
WC
WCR
V
CC
V
SS
Serial Data Address Input/Output
Serial Clock
Write Control
Write Control of Control Register
Supply Voltage
Ground
VCC
SCL
WC
WCR
M34S32
SDA
VSS
AI02468
June 1998
This is a Preliminary Data. Details are subject to change without notice.
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