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M24256-B Datasheet

  • M24256-B

  • 256/128 Kbit Serial I C Bus EEPROM With Three Chip Enable Li...

  • 19頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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M24256-B
M24128-B
256/128 Kbit Serial I C Bus EEPROM
With Three Chip Enable Lines
PRELIMINARY DATA
s
s
Compatible with I
2
C Extended Addressing
Two Wire I
2
C Serial Interface
Supports 400 kHz Protocol
Single Supply Voltage:
鈥?4.5V to 5.5V for M24xxx-B
鈥?2.5V to 5.5V for M24xxx-BW
鈥?1.8V to 3.6V for M24xxx-BR
s
8
1
PSDIP8 (BN)
0.25 mm frame
14
1
TSSOP14 (DL)
169 mil width
s
s
s
s
s
s
s
s
Hardware Write Control
BYTE and PAGE WRITE (up to 64 Bytes)
RANDOM and SEQUENTIAL READ Modes
Self-Timed Programming Cycle
Automatic Address Incrementing
Enhanced ESD/Latch-Up Behavior
100000 Erase/Write Cycles (minimum)
40 Year Data Retention (minimum)
8
1
SO8 (MN)
150 mil width
8
1
TSSOP8 (DW)
169 mil width
DESCRIPTION
These I
2
C-compatible electrically erasable pro-
grammable memory (EEPROM) devices are orga-
nized as 32Kx8 bits (M24256-B) and 16Kx8 bits
(M24128-B).
These memory devices are compatible with the
I
2
C extended memory standard. This is a two wire
serial interface that uses a bi-directional data bus
and serial clock. The memory carries a built-in 4-
bit unique Device Type Identifier code (1010) in
accordance with the I
2
C bus definition.
Figure 1. Logic Diagram
VCC
3
Table 1. Signal Names
E0, E1, E2
SDA
Chip Enable Inputs
Serial Data/Address Input/
Output
Serial Clock
Write Control
Supply Voltage
Ground
E0-E2
SCL
WC
M24256-B
M24128-B
SDA
SCL
WC
V
CC
V
SS
VSS
AI02809
February 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/19

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