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M24256-A Datasheet

  • M24256-A

  • 256 Kbit Serial I C Bus EEPROM With Two Chip Enable Lines

  • 20頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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M24256-A
256 Kbit Serial I C Bus EEPROM
With Two Chip Enable Lines
PRELIMINARY DATA
s
s
Compatible with I
2
C Extended Addressing
Two Wire I
2
C Serial Interface
Supports 400 kHz Protocol
Single Supply Voltage:
鈥?4.5V to 5.5V for M24256-A
鈥?2.5V to 5.5V for M24256-AW
鈥?1.8V to 3.6V for M24256-AR
14
8
1
PSDIP8 (BN)
0.25 mm frame
s
1
TSSOP14 (DL)
169 mil width
s
2 Chip Enable Inputs: up to four memories can
be connected to the same I
2
C bus
Hardware Write Control
BYTE and PAGE WRITE (up to 64 Bytes)
RANDOM and SEQUENTIAL READ Modes
Self-Timed Programming Cycle
Automatic Address Incrementing
Enhanced ESD/Latch-Up Behavior
More than 100,000 Erase/Write Cycles
More than 40 Year Data Retention
SBGA
s
s
s
s
s
s
s
s
SBGA7 (EA)
140 x 90 mil
8
1
SO8 (MN)
150 mil width
8
1
SO8 (MW)
200 mil width
DESCRIPTION
These I
2
C-compatible electrically erasable pro-
grammable memory (EEPROM) devices are orga-
nized as 32Kx8 bits, and operate down to 2.5 V
(for the M24256-AW), and down to 1.8 V (for the
M24256-AR).
The M24256-A is available in Plastic Dual-in-Line,
Plastic Small Outline and Thin Shrink Small Out-
line packages. The M24256-A is also available in
a chip-scale (SBGA) package.
Figure 1. Logic Diagram
VCC
2
E0-E1
Table 1. Signal Names
E0, E1
SDA
SCL
WC
V
CC
V
SS
Chip Enable
Serial Data
Serial Clock
Write Control
Supply Voltage
Ground
SDA
M24256-A
SCL
WC
VSS
AI02271C
April 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/20

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