Integrated
Circuit
Systems, Inc.
Product Data Sheet
M2040
FIN_SEL1
GND
AUTO
DIF_REF0
nDIF_REF0
REF_SEL
DIF_REF1
nDIF_REF1
VCC
27
26
25
24
23
22
21
20
19
F
REQUENCY
T
RANSLATION
PLL
WITH
A
UTO
S
WITCH
P
IN
A
SSIGNMENT
(9 x 9 mm SMT)
G
ENERAL
D
ESCRIPTION
The M2040 is a VCSO (Voltage Controlled SAW
Oscillator) based clock generator
PLL designed for clock protection,
frequency translation and jitter
attenuation in fault tolerant
computing applications. It features
dual differential inputs with two
modes of input selection: manual
and automatic upon clock failure. The clock
multiplication ratios and output divider ratio are
pin selectable. External loop components allow the
tailoring of PLL loop response.
F
EATURES
鈼?/div>
Integrated SAW (surface acoustic wave) delay line;
VCSO frequency of 400.00 or 533.3334 MHz;
*
outputs
VCSO frequency or half; pin-configurable dividers
鈼?/div>
Loss of Lock (LOL) indicator output
鈼?/div>
Narrow Bandwidth control input (NBW Pin);
Initialization (INIT) input overrides NBW at power-up
鈼?/div>
Dual reference clock inputs support LVDS, LVPECL,
LVCMOS, LVTTL
鈼?/div>
Automatic (non-revertive) reference clock reselection
upon clock failure; controlled PLL slew rate ensures
normal system operation during reference reselection
鈼?/div>
Acknowledge pin indicates the actively selected
reference input
鈼?/div>
Dual differential LVPECL outputs
鈼?/div>
Low phase jitter of < 0.5ps rms, typical
(12kHz to 20MHz or 50kHz to 80MHz)
鈼?/div>
Industrial temperature available
鈼?/div>
Single 3.3V power supply
鈼?/div>
Small 9 x 9 mm SMT (surface mount) package
FIN_SEL0
MR_SEL
REF_ACK
LOL
NBW
VCC
DNC
DNC
DNC
28
29
30
31
32
33
34
35
36
M2040
(Top View)
18
17
16
15
14
13
12
11
10
P_SEL
INIT
nFOUT0
FOUT0
GND
nFOUT1
FOUT1
VCC
GND
Figure 1: Pin Assignment
Example Input / Output Frequency Combinations
Input (MHz) VCSO * (MHz)
200.0000
400.0000
213.3333
266.6667
533.3334
284.4444
Output (MHz)
200.0000
400.0000
266.6667
533.3334
Table 1: Example Input / Output Frequency Combinations
* Specify VCSO center frequency at time of order.
S
IMPLIFIED
B
LOCK
D
IAGRAM
Loop Filter
M2040
NBW
MUX
PLL
Phase
Detector
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_ACK
REF_SEL
AUTO
Auto
INIT
LOL
MR_SEL
FIN_SEL1:0
P_SEL
2
Ref Sel
0
R Div
VCSO
1
0
1
M Div
LOL
Phase
Detector
Mfin Divider
GND
GND
GND
OP_IN
nOP_OUT
nVC
VC
OP_OUT
nOP_IN
1
2
3
4
5
6
7
8
9
FOUT0
nFOUT0
M / R Divider
P Divider
Mfin Divider
LUT
LUT
FOUT1
nFOUT1
Figure 2: Simplified Block Diagram
M2040 Datasheet Rev 1.0
M2040 Frequency Translation PLL with AutoSwitch
Revised 28Jan2005
鈼?/div>
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
Networking & Communications
鈼?/div>
w w w. i c s t . c o m
鈼?/div>
tel (508) 852-5400
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