鈥?/div>
Low power consumption
adr[14:0]
din[31:0]
dout[31:0]
bweb[3:0]
rdb
wrb
clk
rstb
mvddcore
mvsscore
mvdd
mvss
General Description
The M1T1HT18PZ32E macro is a 1Mbit (1,084,576 bits), high speed, embedded 1T-SRAM macro. The macro
is organized as 32K(32,768) words of 32 bits. The macro employs a pipelined read timing interface with late
write timing. Write control over individual bytes in the input data is achieved through the use of the byte write
enable (bweb) input signals. The macro is implemented using MoSys 1T -SRAM technology, resulting in
extremely high density and performance.
M1T1HT18PZ32E Rev 2.doc
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