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M13S256328A Datasheet

  • M13S256328A

  • 2M x 32 Bit x 4 Banks Double Data Rate SDRAM

  • 47頁

  • ESMT

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ESMT
DDR SDRAM
Features
JEDEC Standard
Internal pipelined double-data-rate architecture, two data access per clock cycle
Bi-directional data strobe (DQS)
On-chip DLL
Differential clock inputs (CLK and CLK )
DLL aligns DQ and DQS transition with CLK transition
Quad bank operation
CAS Latency : 2; 2.5; 3
Burst Type : Sequential and Interleave
Burst Length : 2, 4, 8, full page
Full page burst length for sequential burst type only
Start address of the full page burst should be even
All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
Data I/O transitions on both edges of data strobe (DQS)
DQS is edge-aligned with data for reads; center-aligned with data for WRITE
Data mask (DM) for write masking only
V
DD
= 2.3V ~ 2.7V, V
DDQ
= 2.3V ~ 2.7V
Auto & Self refresh
64ms refresh period (8K cycle)
SSTL-2 I/O interface
144Ball FBGA package
M13S256328A
2M x 32 Bit x 4 Banks
Double Data Rate SDRAM
Operating Frequencies :
PRODUCT NO.
M13S256328A -5BG
MAX FREQ
200MHz
VDD
2.5V
PACKAGE
144 Ball FBGA
COMMENTS
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.2
1/47

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