Integrated
Circuit
Systems, Inc.
Preliminary Information
M1010-01
VCSO B
ASED
C
LOCK
J
ITTER
A
TTENUATOR
P
IN
A
SSIGNMENT
(9 x 9 mm SMT)
FIN_SEL1
GND
NC
DIF_REF0
nDIF_REF0
REF_SEL
DIF_REF1
nDIF_REF1
VCC
FIN_SEL0
SEL0
SEL1
SEL2
NC
VCC
DNC
DNC
DNC
27
26
25
24
23
22
21
20
19
G
ENERAL
D
ESCRIPTION
The M1010-01 is a VCSO (Voltage Controlled SAW
Oscillator) based clock jitter
attenuator PLL designed for clock
jitter attenuation and frequency
translation. The device is ideal for
generating the transmit reference
clock for OC-12 and OC-48 optical
network systems supporting 622 -
2,488 MHz rates. It can serve to jitter attenuate a
stratum reference clock or a recovered clock in loop
timing mode. The M1010-01 module includes a
proprietary SAW (surface acoustic wave) delay line as
part of the VCSO. This results in a high frequency,
high-Q, low phase noise oscillator that assures low
intrinsic output jitter.
28
29
30
31
32
33
34
35
36
M1010
(Top View)
18
17
16
15
14
13
12
11
10
VCC
NC
nFOUT
FOUT
GND
NC
NC
VCC
GND
F
EATURES
鈼?/div>
Ideal for OC-12/48 data clock
鈼?/div>
Integrated SAW delay line
鈼?/div>
Output frequencies from 150 to 175 MHz
(Specify VCSO output frequency at time of order)
鈼?/div>
Low phase jitter of 0.5 ps rms, typical (12kHz to 20MHz)
鈼?/div>
LVPECL clock output
鈼?/div>
Pin-selectable feedback and reference divider ratios,
no programming required
鈼?/div>
Scalable dividers provide further adjustment of loop
bandwidth as well as jitter tolerance
鈼?/div>
Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
鈼?/div>
Single 3.3V power supply
鈼?/div>
Small 9 x 9 mm SMT (surface mount) package
Figure 1: Pin Assignment
Example I/O Clock Frequency Combinations
Using
M1010-01-155.5200
Frequency
Input (Mfin)
Ratio
8
2
1
Input Reference
Clock
(MHz)
19.44
77.76
155.52
Output
Clock MHz
155.52
Table 1: Example I/O Clock Frequency Combinations
S
IMPLIFIED
B
LOCK
D
IAGRAM
M1010
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_SEL
3
2
0
R Div
1
M Div
Mfin Div
VCSO
Loop
Filter
GND
GND
GND
OP_IN
nOP_OUT
nVC
VC
OP_OUT
nOP_IN
1
2
3
4
5
6
7
8
9
SEL2:0
FIN_SEL1:0
Divider LUT
Mfin Divider
LUT
FOUT
nFOUT
Figure 2: Simplified Block Diagram
M1010-01 Datasheet Rev 0.4
M1010-01 VCSO Based Clock Jitter Attenuator
Revised 29Sep2003
鈼?/div>
Integrated Circuit Systems, Inc.
Communications Modules
鈼?/div>
w w w. i c s t . c o m
鈼?/div>
tel (508) 852-5400
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