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LXT336QE Datasheet

  • LXT336QE

  • PCM RECEIVER|QUAD|CEPT PCM-30/E-1|CMOS|QFP|64PIN|PLASTIC

  • 22頁(yè)

  • ETC

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LXT336
Quad T1/E1 Receiver
Datasheet
The LXT336 quad receiver is a fully-integrated, quadruple-PCM receiver for both T1 (1.544
Mbps) and E1 (2.048 Mbps) applications. It incorporates four independent receivers in a single
64-pin QFP package.
The LXT336 features a differential receiver architecture with high noise interference margin. It
uses peak detection with a variable threshold for reliable recovery of data as low as 500 mV and
up to 12 dB of cable attenuation.
The fully digital clock recovery system uses a low frequency master clock of 2.048 MHz or
1.544 MHz as its reference. In addition, each LXT336 receiver incorporates a Loss of Signal
(LOS) detection circuit. The LOS detector is compliant with both ITU-T G.775 and ANSI
T1.231 standards.
The LXT336 ports can be independently configured for either unipolar or bipolar output modes.
HDB3 and AMI decoding mechanisms are available in unipolar mode.
Applications
s
s
Test Equipment
DSX-1 and E1 Line Monitoring
s
High density T1/E1 line cards
Product Features
s
s
s
s
s
Fully integrated quad, receiver for E1 2.048
Mbps or T1 1.544 Mbps operation
Single rail supply voltage of 5 V (typical)
Low power consumption: 250 mW for E1;
200 mW for T1 (typical)
High-performance receivers recover data
with up to 12 dB cable attenuation
On-chip clock recovery function complies
with ITU G.823 and Bellcore GR-499-
CORE
s
s
s
s
s
s
Low frequency 1.544 or 2.048 MHz
reference clock
Programmable unipolar and bipolar PCM
interface
On-chip AMI and HDB3 decoders
Loss of Signal processors conform to ITU
G.775 and ANSI T1.231 recommendations
Small-footprint 64-pin QFP
Optional RZ Data recovery mode
As of January 15, 2001, this document replaces the Level One document
LXT336 鈥?Quad T1/E1 Receiver.
Order Number: 249046-001
January 2001

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