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SL74LV573

OCTAL D-TYPE TRANSPARENT LATCH (3-State)

By pinning SL74LV573 are compatible with SL74HC573 and

SL74HCT573 series. Input voltage levels are compatible with

stadard CMOS levels.

鈥?/div>

Output voltage levels are compatible with input levels of CMOS,

NMOS and TTL IC

S

鈥?/div>

Voltage supply range from 1.2 to 5.5 V

鈥?/div>

LOW input current: 1.0

碌脌;

0.1

碌脌

at 脪 = 25

擄脩

鈥?/div>

Output current 8 m脌

鈥?/div>

Latch current: not less than150 m脌 at 脪 = 125

擄脩

鈥?/div>

ESD acceptable value: not less than 2000 V as per HBM and

not less than 200 V as per MM

ORDERING INFORMATION

SL74LV573N Plastic DIP

SL74LV573D SOIC

T

A

= -40擄 to 125擄 C

for all packages

FUNCTION TABLE

Inputs

OE

L

H

LE

H

L

X

D

H

L

X

Outputs

Q

H

L

no change

Z

PIN ASSIGNMENT

OE

D0

D1

D2

D3

D4

D5

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

V

CC

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

LE

H -HIGH voltage level

L - LOW voltage level

X - don鈥檛 care

Z - High impedance state

D6

D7

GND

SLS

System Logic

Semiconductor

型號(hào)

版本

描述

廠(chǎng)商

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LV573 Datasheet

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