high-speed serial bit clock. In the 1.0 Gbits/s鈥?/div>
on the falling edge of the low-speed TBC clock. In the
low-speed TBC clock. REFCLK and TBC clock are
relationship is arbitrary. The serialized data is avail-
鈩?/div>
or 75
鈩?
to drive either an optical transmitter or
coaxial media.
The receive section receives high-speed serial data
at its differential CML input port. This data is fed to
the clock recovery section which generates a recov-
ered clock and retimes the data. The retimed data is
deserialized and presented as a 10-bit encoded or a
8-bit unencoded parallel data on the output port.
Two-phase receive byte clocks are available synchro-
nous with the parallel words. The receiver also recog-
nizes the comma characters and aligns the bit
stream to the proper word boundary.
The quad transceiver is controlled and configured
with an 8-bit microprocessor interface. Each channel
has dedicated registers that are readable and writ-
able. The quad device also contains global registers
for control of common circuitry and functions.
Features
s
Designed to operate in Ethernet, fibre channel,
FireWire
*, or backplane applications.
Operationally compliant with the fibre channel
X3T11. Provides FC-0 services at 1.0 Gbits/s鈥?/div>
1.25 Gbits/s, 2.0 Gbits/s鈥?.5 Gbits/s, and
3.125 Gbits/s.
Selectable data rate (1.0 Gbits/s鈥?.25 Gbits/s,
2.0 Gbits/s鈥?.5 Gbits/s, and 3.125 Gbits/s).
100 MHz鈥?56 MHz differential CML or single-
ended CMOS reference clock.
8-bit/10-bit parallel I/O interface.
Programmable control and configuration interface
to define the various device configurations.
Automatic lock to reference in absence of receive
data.
CML high-speed interface I/O for use with optical
transceiver, coaxial copper media, or shielded
twisted pairs.
Programmable transmit pre-emphasis optimized
for backplanes.
Requires one external resistor for bias current gen-
eration.
Requires no external components for clock recov-
ery and frequency synthesis.
Under 250 mW per transceiver.
Low powerdown dissipation.
1.5 V 鹵 5% power supply.
1.8 V 鹵 5% power supply option for differential high
speed I/O circuits.
鈥?0 擄C鈥?0 擄C ambient temperature.
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
Potential Applications
s
s
Stand-alone transceiver product.
Transceiver macrocell template.
*
FireWire
is a registered trademark of Apple Computer, Inc.
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