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Preliminary Data Sheet

July 2000

LU5X34F

Quad Gigabit Ethernet Transceiver

Overview

The LU5X34F is a low-cost, low-power quad trans-

ceiver. It is used for data transmission over fiber or

coaxial media in conformance with

IEEE

* 802.3z

Gigabit Ethernet specification and Fibre Channel

ANSI

鈥?/div>

X3T11 at 1.0 Gbits/s and

1.25 Gbits/s.

Each of the four transceivers independently provides

complete serialize/deserialize (SERDES) and trans-

mit and receive functions. The device is available in a

217-pin PBGA package.

The transmitter section accepts TTL compatible data

at the 10-bit parallel input port. The parallel input

data is latched on the rising edge of TXCLKx. It also

accepts the low-speed, TTL compatible system

clock, REFCLK, and uses this clock to synthesize the

internal high-speed serial bit clock. The serialized

data is then available at the differential PECL out-

puts, terminated in 50

鈩?/div>

or 75

鈩?/div>

to drive either an

optical transmitter or coaxial media.

The receive section receives high-speed serial data

at its differential PECL input port. This data is fed to

the digital clock recovery section, which generates a

recovered clock and retimes the data. The retimed

data is deserialized and presented as 10-bit parallel

data on the output port. A divided-down version of

the recovered clock, synchronous with parallel data

bytes, is also available as a TTL compatible output.

The receive section recognizes the comma character

and aligns the comma-containing byte on the word

boundary, when ENCDET = 1.

s

100 MHz鈥?25 MHz differential or single-ended

reference clock.

10-bit parallel, TTL-compatible I/O interface.

8-bit/10-bit encoded data.

High-speed comma character recognition (K28.1,

K28.5, K28.7) for latency-sensitive applications

and alignment to word boundary.

Two 50 MHz鈥?2.5 MHz receive-byte clocks.

Single analog PLL design requires no external

components for the frequency synthesizer.

Novel digital data lock in receiver avoids the need

for multiple analog PLLs.

Expandable beyond four serializer/deserializers.

PECL high-speed interface I/O for use with optical

transceiver or coaxial copper media.

Requires one external resistor for PECL output ref-

erence-level definition.

Low-power digital CMOS technology.

Less than 2 W total power dissipation per quad

transceiver.

3.3 V 鹵 5% power supply.

0 擄C鈥?0 擄C ambient temperature.

Stand-alone transceiver product.

Transceiver macrocell template.

Available in 217-pin PBGA package.

s

Features

s

Designed to operate in Ethernet, fibre channel,

Firewire

鈥?/div>

, or backplane applications.

Operationally compliant to

IEEE

802.3z Gigabit

Ethernet specification.

Operationally compliant to Fibre Channel

ANSI

X3T11. Provides FC-0 services at 1.0 Gbits/s鈥?/div>

1.25 Gbits/s (10-bit encoded data rate).

*

IEEE

is a registered trademark of The Institute of Electrical and

Electronics Engineers, Inc.

鈥?/div>

ANSI

is a registered trademark of American National Standards

Institute.

鈥?/div>

FireWire

is a registered trademark of Apple Computer, Inc.

s

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LU5X34F

英文版

Quad Gigabit Ethernet Transceiver

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LU5X34F
LU5X34F

英文版

Quad Gigabit Ethernet Transceiver

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LU5X34F

LU5X34F Datasheet

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