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X3.263 TP-PMD to
IEEE
摟
802.3 Ethernet specifications.
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100 Mbits/s PLL, combined with the digital adap-
tive equalizer, robustly handles variations in rise-
fall time, excessive attenuation due to channel
loss, duty-cycle distortion, crosstalk, and baseline
wander
Transmit rise-fall time can be manipulated to pro-
vide lower emissions, amplitude fully compatible
for proper interoperability
Programmable scrambler seed for better FCC
compliancy
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IEEE
802.3u Clause 28 compliant autonegotiation
for full 10 Mbits/s and 100 Mbits/s control
Fully configurable via pins and management
accesses
Extended management support with interrupt
capabilities
PHY MIB support
Symbol mode option
Low-power operation: <150 mA max
Low autonegotiation power: <30 mA
Very low powerdown mode: <5 mA
64-pin TQFP package (10 mm x 10 mm x 1.4 mm)
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Features
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Single-chip integrated physical layer and trans-
ceiver for 10Base-T and/or 100Base-T functions
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IEEE
802.3 compatible 10Base-T and 100Base-T
physical layer interface and
ANSI
X3.263 TP-PMD
compatible transceiver
Built-in analog 10 Mbits/s receive filter, eliminating
the need for external filters
Built-in 10 Mbits/s transmit filter
10 Mbits/s PLL exceeding tolerances for both pre-
amble and data jitter
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*
ISO
is a registered trademark of The International Organization
for Standardization.
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EIA
is a registered trademark of The Electronic Industries Asso-
ciation.
鈥?/div>
ANSI
is a registered trademark of The American National Stan-
dards Institute, Inc.
摟
IEEE
is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
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