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LTC2230CUP Datasheet

  • LTC2230CUP

  • Electrical Specifications Subject to Change

  • 28頁

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Electrical Specifications Subject to Change
LTC2230/LTC2231
10-Bit,170Msps/
135Msps ADCs
FEATURES
鈻?/div>
鈻?/div>
鈻?/div>
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DESCRIPTIO
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Sample Rate: 170Msps/135 Msps
61dB SNR up to 140MHz Input
75dB SFDR up to 200MHz Input
775MHz Full Power Bandwidth S/H
Single 3.3V Supply
Low Power Dissipation: 890mW/660mW
LVDS, CMOS, or Demultiplexed CMOS Outputs
Selectable Input Ranges:
鹵0.5V
or
鹵1V
No Missing Codes
Optional Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Data Ready Output Clock
Pin Compatible Family
170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit)
135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit)
64-Pin 9mm x 9mmQFN Package
The LTC
廬
2230 and LTC2231 are 170Msps/135Msps, sam-
pling 10-bit A/D converters designed for digitizing high
frequency, wide dynamic range signals. The LTC2230/
LTC2231 are perfect for demanding communications
applications with AC performance that includes 61dB SNR
and 75dB spurious free dynamic range for signals
up to 200MHz. Ultralow jitter of 0.15ps
RMS
allows
undersampling of IF frequencies with excellent noise
performance.
DC specs include
鹵0.2LSB
INL (typ),
鹵0.1LSB
DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.12LSB
RMS
.
The digital outputs can be either differential LVDS, or
single-ended CMOS. There are three format options for
the CMOS outputs: a single bus running at the full data rate
or two demultiplexed buses running at half data rate with
either interleaved or simultaneous update. A separate
output power supply allows the CMOS output swing to
range from 0.5V to 3.3V.
The ENC
+
and ENC
鈥?/div>
inputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL, or CMOS
inputs. An optional clock duty cycle stabilizer allows high
performance at full speed for a wide range of clock duty
cycles.
APPLICATIO S
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Wireless and Wired Broadband Communication
Cable Head-End Systems
Power Amplifier Linearization
Communications Test Equipment
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATIO
REFH
REFL
FLEXIBLE
REFERENCE
3.3V
V
DD
0.5V
TO 3.3V
OV
DD
SFDR (dBFS)
+
ANALOG
INPUT
INPUT
S/H
鈥?/div>
10-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
OUTPUT
DRIVERS
D9
鈥?/div>
鈥?/div>
鈥?/div>
D0
CMOS
OR
LVDS
OGND
CLOCK/DUTY
CYCLE
CONTROL
22301 TA01
ENCODE INPUT
22301p
U
SFDR vs Input Frequency
90
85
80
75
70
65
60
55
50
45
40
0
100
300
500
200
400
INPUT FREQUENCY (MHz)
600
2nd OR 3rd
4th OR HIGHER
2230 TA01b
U
U
1

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