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LTC1654I Datasheet

  • LTC1654I

  • Linear Technology [Dual 14-Bit Rail-to-Rail DAC in 16-Lead ...

  • 157.91KB

  • LINER

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Final Electrical Specifications
LTC1654
Dual 14-Bit Rail-to-Rail DAC
in 16-Lead SSOP Package
FEATURES
s
s
April 2000
DESCRIPTIO
s
s
s
s
s
s
s
14-Bit Monotonic Over Temperature
Individually Programmable Speed/Power:
3.5碌s Settling Time at 750碌A
8碌s Settling Time at 450碌A
Maximum Update Rate: 0.9MHz
Smallest Dual 14-Bit DAC: 16-Lead Narrow
SSOP Package
Buffered True Rail-to-Rail Voltage Outputs
3V to 5V Single Supply Operation
User Selectable Gain
Power-On Reset and Clear Function
Schmitt Trigger On Clock Input Allows Direct
Optocoupler Interface
The LTC
1654 is a dual, rail-to-rail voltage output, 14-bit
digital-to-analog converter (DAC). It is available in a
16-lead narrow SSOP package, making it the smallest dual
14-bit DAC available. It includes output buffer amplifiers
and a flexible serial interface.
The LTC1654 has REFHI pins for each DAC that can be
driven up to V
CC
. The output will swing from 0V to V
CC
in
gain of 1 configuration or V
CC
/2 in gain of 1/2 configura-
tion. It operates from a single 2.7V to 5.5V supply.
The LTC1654 has two programmable speeds: a FAST and
SLOW mode with
鹵1LSB
settling times of 3.5碌s or 8碌s
respectively and supply currents of 750碌A and 450碌A in
the two modes. The LTC1654 also has shutdown capabil-
ity, power-on reset and clear function to 0V.
, LTC and LT are registered trademarks of Linear Technology Corporation.
APPLICATIO S
s
s
s
s
Digital Calibration
Industrial Process Control
Automatic Test Equipment
Offset/Gain Adjustment
BLOCK DIAGRA
CS/LD
SCK
CONTROL
LOGIC
SDI
INPUT
LATCH
DAC
REGISTER
DAC B
+
V
OUT B
鈥?/div>
32-BIT
SHIFT
REGISTER
X
1
/X
1/2
B
REFHI A
INPUT
LATCH
DAC
REGISTER
DAC A
+
V
OUT A
SDO
POWER-ON
RESET
REFLO B
REFLO A
鈥?/div>
X
1
/X
1/2
A
1654 BD
CLR
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
REFHI B
W
U
1

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