鈥?Builds upon proven technology 鈥?/div>
A pin-for-pin replacement for
the industry standard
LSI53C810 and LSI53C810AE
鈥?Easy migration minimizes
schedule and design risk
OVERVIEW
The LSI53C860E controller supports Ultra SCSI transfers, enabling the
chip to transfer SCSI data at up to 20 MBps across an 8-bit SCSI bus. Ultra
SCSI doubles the synchronous transfer rates of Fast SCSI. The advantage of
LSI Logic鈥檚 Ultra SCSI is that it significantly improves SCSI bandwidth, while
preserving existing hardware and software investments. The LSI53C860E
provides full SCSI-2 capabilities, including command queuing, and features
TolerANT SCSI driver and receiver technology, for reliable operation in all
cabling environments. It is designed to connect to the Peripheral Component
Interconnect (PCI) bus, performing burst transfers on the bus in excess of
110 MBps.
廬
鈥?Provides new features for
enhanced PCI performance
and flexibility
FEATURES
鈥?Performs high-speed single-
ended SCSI bus transfers up to:
鈥?20 MBps synchronous Ultra
SCSI transfers
鈥?7 MBps asynchronous transfers
鈥?SCRIPTS
鈩?/div>
Instruction Prefetch
鈥?Load and Store instruction
鈥?Support for PCI Cache Line
Size Register
鈥?Functions as full 32-bit PCI
DMA bus master
鈥?Bursts 2, 4, 8, or 16 dwords of
data across PCI bus using
80-byte DMA FIFO
The LSI53C860E controller and Storage Device Management System
(SDMS
鈩?/div>
) software, provide a total Ultra SCSI solution in PC and workstation
environments. LSI Logic鈥檚 SDMS software package supports the entire
LSI53C8XX family of PCI to SCSI controllers, plus a wide range of SCSI
peripheral devices.
PCI performance enhancements on the LSI53C860E include the SCRIPTS
(the LSI Logic developed SCSI programming language) instruction prefetch,
which when enabled, permits fetching four or eight double words of instruc-
tions or instruction operands. By pre-fetching instructions, the LSI53C860E
makes more efficient use of the PCI system bus by reducing the PCI bus over-
head requirements. In addition, the part supports the PCI Cache Line Size
Register with programmable alignment logic and automatic burst sizing,
allowing system architects to maximize their cache-based system performance
1
2
3
4
