鈩?/div>
processor for maximum capability
鈥?Provides new features for
OVERVIEW
The LSI53C810AE controller is a single-chip high-performance Fast
SCSI I/O processor. It is designed to connect gluelessly to the Peripheral
Component Interconnect (PCI) bus. A drop-in replacement for the industry
standard LSI53C810, the LSI53C810AE transfers 8-bit SCSI data at speeds
as high as 7 MBps asynchronous and 10 MBps synchronous, while adding
features to further improve performance and enhance flexibility. The device
performs burst transfers on the PCI bus in excess of 110 MBps. The
LSI53C810AE provides full SCSI-2 capabilities, including command queuing,
and features LSI Logic鈥檚 TolerANT SCSI driver and receiver technology, for
reliable operation in all cabling environments.
廬
enhanced PCI performance
and flexibility
FEATURES
鈥?SCRIPTS Instruction Prefetch
鈥?Load and store instruction
鈥?Support for PCI Cache Line
Size Register
鈥?Performs high-speed single-
ended SCSI bus transfers up to:
鈥?10 MBps synchronous
鈥?7 MBps asynchronous
鈥?Functions as full 32-bit PCI
DMA bus master
鈥?Bursts 2, 4, 8, or 16 dwords of
data across PCI bus using
80-byte DMA FIFO
The LSI53C810AE controller along with the SDMS
鈩?/div>
software, provides
a total SCSI solution in PC and workstation environments. LSI Logic鈥檚 SDMS
software package supports the entire LSI53C8XX family of PCI to SCSI
controllers, plus a wide range of SCSI peripheral devices.
PCI performance enhancements on the LSI53C810AE include the
SCRIPTS (the LSI Logic developed SCSI programming language) instruction
prefetch, which when enabled, permits fetching four or eight double words
of instructions or instruction operands. By pre-fetching instructions, the
LSI53C810AE makes more efficient use of the PCI system bus by reducing
the PCI bus overhead requirements. In addition, the part supports the PCI
Cache Line Size Register with programmable alignment logic and automatic
burst sizing, allowing system architects to maximize their cache-based system
performance through efficient use of PCI Memory Read Line, Memory Read
Multiple, and Memory Write and Invalidate access cycles. Other selectable
features that can be activated include:
鈥?IRQ disable, allowing users to better control the times when their system
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