鈥?/div>
IEEE 1149.1-compliant JTAG port
MEMORY
The internal memory structure of the LSI403Z comprises of 16K words of
on-chip instruction memory, 16K words of on-chip data memory, 2K words on-
chip boot ROM, and on-chip peripherals. Additionally, the boot ROM provides
start-up and self-test capabilities. Both synchronous and asynchronous devices
are supported including sync-burst SRAM. The external memory is logically
segmented into instruction, data, and peripheral spaces.
for real-time emulation
BENEFITS
鈥?/div>
300 MMAC sustained DSP
DMA
The DMA controller of the LSI403Z supports zero-overhead instruction or data
transfers to or from the entire 32K words of internal RAM to the memory interface
unit, host processor interface, or serial ports. The eight DMA channels are
segmented between four 鈥渋ndexed鈥?and four 鈥渘on-indexed鈥?channels. Indexed
channels have the ability to multiplex and de-multiplex data. Indexed channels can
also operate in non-indexed mode.
performance at 150 MHz
鈥?/div>
Direct interfacing to standard
telecommunications interfaces,
reducing system cost
鈥?/div>
High data throughput without
processor overhead
鈥?/div>
Low power per channel
鈥?/div>
Flexibility to optimize power
JTAG
PPL
Boot ROM
Program
Memory
16Kx16
Data
Memory
16Kx16
Instruction Unit
I-Cache
Data Unit
D-Cache
64b
consumption
ICU
64b
32b
DEU
Pipeline
Control
Unit
DSP Core
Register File
ALU 1
ALU 2
MAC 1
鈥?/div>
High data bandwidth to off-chip
devices
鈥?/div>
RTOS support and increased
system integration
鈥?/div>
Low overhead on chip debug
鈥?/div>
Ideal for Voice over DSL IAD designs
64b
32b
64b
32b
Bus I/F Unit
MAC 2
DMA
MXU
HPI
PIO
The
Communications
Company
TM
Load/Store Buffer Serial Port 0 Serial Port 1
Xbus
Figure 1. LSI403Z Functional Block Diagram
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