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LS7266R1 Datasheet

  • LS7266R1

  • 24-BIT DUAL-AXIS QUADRATURE COUNTER

  • 74.23KB

  • 14頁

  • LSI

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UL
廬
LSI/CSI
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747
YLCNTR/YLOL
FCK
1
2
V
DD
(+5V) 3
D0
D1
D2
D3
D4
D5
D6
D7
4
5
6
7
8
9
10
11
LS7266R1
(631) 271-0400 FAX (631) 271-0405
December 2002
PIN ASSIGNMENT - TOP VIEW
28-Pin Package
28
27
26
25
24
23
22
21
20
19
18
17
16
15
YRCNTR/YABG
YFLG1
YFLG2
YA
YB
XFLG2
XFLG1
XB
XA
XLCNTR/XLOL
XRCNTR/XABG
X/Y
RD
CS
A3800
24-BIT DUAL-AXIS QUADRATURE COUNTER
FEATURES:
鈥?30 MHz count frequency in non-quadrature mode,
17MHz in x4 quadrature mode.
鈥?Dual 24-bit counters to support X and Y axes in
motion control applications.
鈥?Dual 24-bit comparators.
鈥?Digital filtering of the input quadrature clocks
鈥?Programmable 8-bit separate filter clock prescalers
for each axis.
鈥?Error flags for noise exceeding filter band width.
鈥?Programmable Index Input and other programmable I/Os.
鈥?Independent mode programmability for each axis.
鈥?Programmable count modes:
Quadrature (x1, x2, x4) / Non-quadrature,
Normal / Modulo-N / Range Limit / Non-Recycle,
Binary / BCD.
鈥?8-bit 3-State data I/O bus.
鈥?5V operation (V
DD
-V
SS
).
鈥?TTL/CMOS compatible I/Os.
鈥?LS7266R1 (DIP); LS7266R1-SD (Skinny DIP);
LS7266R1-S (SOIC); LS7266R1-TS (TSSOP)
LS72 66R1
V
SS
(GND) 12
C/D 13
WR 14
LS7266R1 Registers:
LS7266R1 has a set of registers associated with each X and Y axis. All X-axis registers have the name prefix X,
whereas all Y-axis registers have the prefix Y. Selection of a specific register for Read/Write is made from the decode
of the three most significant bits (D7-D5) of the data-bus. CS input enables the IC for Read/Write. C/D input selects
between control and data information for Read/Write. Following is a complete list of LS7266R1 registers.
Preset Registers: XPR and YPR
Each of these PRs are 24-bit wide. 24-bit data can be written into a PR, one byte at a time, in a sequence of three data
write cycles.
PR
7
HI BYTE
(PR2)
0 7
MID BYTE
(PR1)
0 7
0
LO BYTE
(PR0)
Counters: XCNTR and YCNTR
Each of these CNTRs are 24-bit synchronous Up/Down counters. The count clocks for each CNTR is derived from its
associated A/B inputs. Each CNTR can be loaded with the content of its associated PR.
Output Latches: XOL and YOL
Each OL is 24-bits wide. In effect, the OLs are the output ports for the CNTRs. Data from each CNTR can be loaded
into its associated OL and then read back on the data-bus, one byte at a time, in a sequence of three data Read
cycles.
OL
7
HI BYTE
(OL2)
0 7
MID BYTE
(OL1)
0 7
0
LO BYTE
(OL0)
Byte Pointers: XBP and YBP
The Read and Write operations on an OL or a PR always accesses one byte at a time. The byte that is accessed is
addressed by one of the BPs. At the end of every data Read or Write cycle on an OL or a PR, the associated BP is
automatically incremented to address the next byte.
7266R1-121002-1

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