LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747
鈥?/div>
Programmable Delay from 6 ms to "Infinity"
鈥?Can be Cascaded for Sequential Events or Extended Delay
鈥?+4.75V to +15V Operation (Vss -V
DD
)
鈥?On Chip Oscillator or External Clock time base
鈥?High Noise Immunity
鈥?LS7210 (DIP), LS7210-S (SOIC)-See Figure 1
DESCRIPTION:
The LS7210 is a monolithic MOS integrated circuit programmable
digital timer that can generate a delay in the range of 6ms to infinity.
The delay is programmed by 5 binary weighted input bits in combina-
tion with the time base provided. The chip can be operated in four
different modes: Delayed Operate, Delayed Release, Dual Delay
and One Shot. These modes are selected by the control inputs A
and B.
INPUT/OUTPUT DESCRIPTION:
OSCILLATOR Input
(Pin 5)
The frequency of the internal oscillator is set by an RC network con-
nected to the OSC input, as shown in Figure 2. The nominal os-
cillator frequency, f, at room temperature is given by f鈮?/RC where R
values range from a minimum of 47K鈩?to a maximum 3M鈩?
NOTE:
Oscillation accuracy from chip to chip for a fixed value of RC,
is + 10%. (Parts can supplied to tighter tolerances.)
B
1
A
2
3
14
13
12
V
SS
(+V)
OUT
WB0
WB1
WB2
WB3
WB4
LSI
LS7210
FIGURE 1
4
5
11
10
9
8
6
7
TABLE 1. WEIGHTING BITS ASSIGNMENTS
INPUTS
WB0
WB1
WB2
WB3
WB4
VALUE
1
2
4
8
16
Example:
For a weighting factor of 25, inputs WB4, WB3, and
EXTERNAL CLOCK Input
(Pin 6)
WB0 should be programmed to logic 0.
If the internal oscillator is not used, the chip can be driven by an ex-
ternal clock applied to this input.
MODE SELECT Inputs A, B
(Pins 2, 1)
The chip can be programmed to operate in four different modes
CLOCK SELECT Input
(Pin 4)
by applying the logic levels to inputs A and B as indicated in
The internal oscillator or the external clock is selected by the proper Table 2. The mode select inputs are clocked into the input latch-
logic level applied to this input. A logic 1 selects the external clock es with the negative edge of the time base clock. These inputs
and logic 0 selects the internal oscillator. (See Note 1)
should not be changed while a delay timing is in progress. (See
Note 1)
TRIGGER Input
(Pin 3)
TABLE 2. MODE SELECTION
A positive or a negative transition at the trigger input initiates a delay
in turning on or off the output. A negative transition always turns on
CONTROL
MODE
the output with or without delay depending on the selected mode. A
A
B
positive transition at the trigger input always turns off the output (with
1
1
Dual Delay
the exception of one-shot mode) with or without delay depending on
1
0
Delayed Release
the selected mode. The delay is a function of the time base fre-
0
1
Delayed Operate
quency and the weighting factor programmed at the weighting bit in-
0
0
One Shot
puts. The trigger input is clocked into the input latch with the neg-
ative edge of the selected time base clock. All timings begin after the
OUT Output
(Pin 13)
latch has been set up. (See Note 1)
The output is an open drain FET. To obtain proper switching of
the output between Logic 0 and 1 levels, an external pull down re-
sistor to V
DD
must be used. If the output is used only as a current
WEIGHTING FACTOR Inputs, WB0-WB4
(Pins 12-8)
source, no such pull down is needed. The output is logically in-
A delay from the trigger input to the output is programmed by ap- verted with respect to the trigger input.
plying 1's complement binary weighted numbers at these 5 inputs.
(See Note 1) The exact equation for the delay is:
V
SS
, V
DD
(Pins 14, 9)
Supply voltage positive, negative terminals.
(1 + 1, 023N)
f
= Oscillation Frequency
Delay
=
NOTE 1:
These inputs have internal pullup resistors.
f
N
= Weighting Factor
7210-041700-1
1
2
3
4
