LSI/CSI
UL
廬
LS7061/7063
(631) 271-0400 FAX (631) 271-0405
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747
A3800
Aug. 1998
32 BIT/DUAL 16 BIT BINARY UP COUNTER
WITH BYTE MULTIPLEXED THREE-STATE OUTPUTS
FEATURES:
鈥?DC to 15 MHz Count Frequency
鈥?Byte Multiplexer
鈥?DC to 1 MHz Scan Frequency
鈥?+4.75V to +5.25V Operation (V
DD
-V
SS
)
鈥?Latch Provided for External High Speed Counter Byte,
Effectively Extending Count Frequency to 3.84GHz
鈥?Three-State Data Outputs, Bus and TTL Compatible
鈥?Inputs TTL and CMOS Compatible
鈥?Unique Cascade Feature Allows Multiplexing of
Successive Bytes of Data in Sequence in Multiple
Counter Systems
鈥?LS7061, LS7063 (DIP); LS7061-S, LS7063-S (SOIC)
(See Figures 1 & 2)
DESCRIPTION:
The LS7061/LS7063 is a monolithic, ion implanted MOS Silicon
Gate, 32 bit/dual 16 bit up counter. The IC includes 40 latches,
multiplexer, eight three-state binary data output drivers and out-
put cascading logic.
DESCRIPTION OF OPERATION:
32 (16) BIT BINARY UP COUNTER -
LS7061 (LS7063)
The 32 (16) bit static ripple through counter increments on the
negative edge of the input count pulse. Maximum ripple time is
4碌s (2碌s) - transition count of 32 (16) ones to 32 (16) zeros.
Guaranteed count frequency is DC to 15MHz.
See Figure 8A (8B) for Block Diagram.
COUNT -
LS7061,
COUNT A
- LS7063
Input count pulses to the 32 (first 16) bit counter may be applied
through this input. This input is the most significant bit of the ex-
ternal data byte.
COUNT B -
LS7063
Count pulses may be applied to the last 16 bits of the binary
counter through this input. The counter advances on the negative
transition of these pulses.
RESET
All 32 counter bits are reset to zero when RESET is brought low
for a minimum of 1碌s. RESET must be high for a minimum of
300ns before next valid count can be recorded. COUNT B must
be held low when RESET is brought low to ensure proper reset of
Counter B for LS7063.
TEST COUNT -
LS7061
Count pulses may be applied to the last 16 bits of the binary
counter through this input, as long as Bit 16 of the counter is a
low. The counter advances on the negative transition of these
pulses. This input is intended to be used for test purposes.
PIN ASSIGNMENT - TOP VIEW
PIN ASSIGNMENT - TOP VIEW
LSI
LS7061
FIGURE 1
V
DD
(+V)
(COUNT) B7 IN
B3 OUT
B6 IN
B2 OUT
B5 IN
B1 OUT
B4 IN
B0 OUT
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
15
14
13
B4 OUT
B5 OUT
B0 IN
B1 IN
B6 OUT
B2 IN
B7 OUT
B3 IN
TEST COUNT
SCAN RESET/LOAD
ENABLE
SCAN
R E S E T 10
CASCADE ENABLE OUT 11
Vss (-V) 12
V
DD
(+V)
(COUNTA) B7 IN
B3 OUT
B6 IN
B2 OUT
B5 IN
B1 OUT
B4 IN
B0 OUT
RESET
CASCADE ENABLE OUT
Vss (-V)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
FIGURE 2
B4 OUT
B5 OUT
B0 IN
B1 IN
B6 OUT
B2 IN
B7 OUT
B3 IN
COUNT B
SCAN RESET/LOAD
ENABLE
SCAN
LATCHES -
LS7061 (LS7063)
40 bits of latch are provided, eight for storage of the contents
of a high speed external prescaling counter and the remaining
32 for the contents of the counter data. All latches are loaded
when the LOAD input is brought low for a minimum of 1碌s
and kept low until a minimum of 4碌s (2碌s) has elapsed from
previous negative edge of count pulse (ripple time). Storage
of valid data occurs when LOAD is brought high for a mini-
mum of 250ns before next negative edge of count pulse or
RESET.
LSI
LS7063
7061/63-083198-1
1
2
3
4
5
6
7
