SL74LS164
8-Bit Serial-Input/Parallel-Output
Shift Register
This 8-bit shift register features gated serial inputs and an
asynchronous reset. The gated serial inputs (A and B) permit complete
control over incoming data as a low at either (or both) input(s) inhibits
entry of the new data and resets the first flip flop to the low level at the
next clock pulse. A high level input enables the other input which will
then determine the state of the first flip-flop. Data at the serial inputs
may be changed while the clock is high or low, but only information
meeting the setup requirements will be entered clocking occurs or the
low-to-high level transition of the clock input. All inputs are diode-
clamped to minimize transmission-line effects.
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Gated (Enable/Disable) Serial Inputs
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Fully Buffered Clock and Serial Inputs
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Asynchronous Clear
ORDERING INFORMATION
SL74LS164N Plastic
SL74LS164D SOIC
T
A
=0擄 to 70擄C
for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Reset
L
H
H
PIN 14 =V
CC
PIN 7 = GND
H
H
Clock
X
A1 A2
X X
X X
H D
D H
L L
Outputs
Q
A
Q
B
... Q
H
L
L ... L
no change
D Q
An
... Q
Gn
D Q
An
... Q
Gn
L Q
An
... Q
Gn
D = data input
X = don鈥檛 care
Q
An
- Q
Gn
= data shifted from the previous stage on a
rising edge at the clock input.
SLS
System Logic
Semiconductor
1
2
3
4
