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LRS1341 Datasheet

  • LRS1341

  • Stacked Chip 16M Flash Memory and 2M SRAM

  • 199.06KB

  • 24頁

  • SHARP

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LRS1341/LRS1342
Data Sheet
FEATURES
鈥?Flash Memory and SRAM
鈥?Stacked Die Chip Scale Package
鈥?72-ball CSP (FBGA072-P-0811) plastic package
鈥?Power supply: 2.7 V to 3.6 V
鈥?Operating temperature: -25擄C to +85擄C
鈥?Flash Memory
鈥?Access time (MAX.): 100 ns
鈥?Operating current (MAX.):
The current for F-V
CC
pin
鈥?Read: 25 mA (t
CYCLE
= 200 ns)
鈥?Word write: 17 mA
鈥?Block erase: 17 mA
鈥?Deep power down current (the current for
F-V
CC
pin): 10 碌A (MAX. F-CE
鈮?/div>
F-V
CC
- 0.2 V,
F-RP
鈮?/div>
-0.2 V, F-V
PP
鈮?/div>
0.2 V)
鈥?Optimized array blocking architecture
鈥?Two 4K-word boot blocks
鈥?Six 4K-word parameter blocks
Stacked Chip
16M Flash Memory and 2M SRAM
鈥?Thirty-one 32K-word main blocks
鈥?Top/Bottom boot location versions
鈥?Extended cycling capability
鈥?100,000 block erase cycles
鈥?Enhanced automated suspend options
鈥?Word write suspend to read
鈥?Block erase suspend to word write
鈥?Block erase suspend to read
鈥?SRAM
鈥?Access time (MAX.): 85 ns
鈥?Operating current (MAX.):
鈥?45 mA
鈥?8 mA (t
RC
, t
WC
= 1 碌s)
鈥?Standby current: 45 碌A (MAX.)
鈥?Data retention current: 35 碌A (MAX.)
DESCRIPTION
The LRS1341/LRS1342 is a combination memory
organized as 1,048,576 脳 16-bit flash memory and
131,072 脳 16-bit static RAM in one package.
PIN CONFIGURATION
72-BALL FBGA
INDEX
TOP VIEW
1
A
B
C
D
E
F
G
H
NC
NC
2
NC
3
NC
A
16
F-WE
4
A
11
A
8
F-RY/
BY
5
A
15
A
10
T
1
T
2
6
A
14
A
9
T
3
T
4
7
A
13
8
A
12
9
GND
10
NC
DQ
7
DQ
5
11
NC
12
NC
DQ
15
S-WE
DQ
14
DQ
13
DQ
6
DQ
4
GND
F-WP
F-RP
DQ
12
S-CE
2
S-V
CC
F-V
CC
T
5
DQ
9
DQ
10
DQ
2
DQ
8
DQ
0
DQ
3
DQ
1
F-V
PP
F-A
19
DQ
11
NC
S-LB S-UB
S-OE
F-A
18
NC
NC
F-A
17
A
5
A
7
A
4
A
6
A
0
A
3
F-CE
A
2
A
1
S-CE
1
NC
NC
NC
GND F-OE
NOTE:
Two NC pins at the corner are connected.
LRS1342-1
Figure 1. LRS1341/LRS1342 Pin Configuration
Data Sheet
1

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