鈥?0.6 碌A TYP. (T
鈮?/div>
S-V
CC
- 0.2 V)
鈥?Fully static operation
鈥?Three-state output
NOTES:
1. Block erase and word write operations of flash memory with
T
A
< -30擄C are not supported.
2. Total standby current is the summation of flash鈥檚 memory standby
current and SRAM鈥檚 one.
Stacked Chip
8M Flash Memory and 2M SRAM
PIN CONFIGURATION
48-PIN TSOP
TOP VIEW
S-A
16
/F-A
15
S-A
15
/F-A
14
S-A
14
/F-A
13
S-A
13
/F-A
12
S-A
12
/F-A
11
S-A
11
/F-A
10
S-A
10
/F-A
9
S-A
9
/F-A
8
S-OE
F-WE
F-RP
F-V
PP
S-V
CC
F-WP
F-A18
F-A17
S-A
8
/F-A
7
S-A
7
/F-A
6
S-A
6
/F-A
5
S-A
5
/F-A
4
S-A
4
/F-A
3
S-A
3
/F-A
2
S-A
2
/F-A
1
S-A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
S-A
17
/F-A
16
I/O
15
I/O
7
I/O
14
S-CE
I/O
6
I/O
13
I/O
5
I/O
12
I/O
4
F-V
CC
I/O
11
I/O
3
I/O
10
I/O
2
I/O
9
I/O
1
S-WE
I/O
8
I/O
0
F-OE
GND
F-CE
S-A
1
/F-A
0
DESCRIPTION
The LRS1338A is a combination memory organized
as 524,288 脳 16-bit flash memory and 262,144 脳 8-bit
static RAM in one package. It is fabricated using silicon-
gate CMOS process technology.
LRS1338A-1
Figure 1. LRS1338A Pin Configuration
Data Sheet
1