Load Balance Controller, EZ1900 and
LP2951 + StP8 Regulator
August 28, 2000
AN96-5
TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com
Using the Load Balance Controller, EZ1900, with an LP2951 & StP8
Combination Regulator for a Flexible Motherboard Design
Introduction
The EZ1900 load balance controller is a flexible, low
cost device, providing an automatic power supply up-
grade from single to split-voltage plane processors,
when used with two low dropout regulators. Single
plane processors, such as the Intel Pentium
廬
Proces-
sor P54C, Cyrix 6x86鈩? AMD AMD5
K
86鈩?and the
PowerPC鈩?require a single supply voltage, normally
3.3 or 3.5V.
New split plane processors, such as the Pentium P55C
and versions of the 6x86, AMD5
K
86 & PowerPC
603/604EV require two supply voltages: V
I/O
for the I/O
circuitry, at 3.3 or 3.5V; and V
CC2
for the CPU core, at
between 2.5 and 2.8V.
The EZ1900 can be used with almost any type of
voltage regulator. Application note AN96-4 describes
how to use the EZ1900 with a three- or five-terminal low
dropout regulator. This application note describes how
VIN
R14 (See Table1)
to use the EZ1900 with Semtech鈥檚 low cost LP2951 &
StP8 discrete regulator combination to provide an auto-
matic upgrade path, avoiding costly production
changes or jumpers for different processors.
Principle of Operation
In split plane operation, the EZ1900 switches the output
of the slave regulator to the higher voltage required for
I/O .
When operating in single plane mode, the EZ1900
controls the output of the slave regulator to provide a
lower voltage for V
CC2
, sharing current with the master
for processors whose I/O and core power planes are
connected together. In this mode the two regulators鈥?/div>
operate as master and slave.
Microprocessors, such as those listed above, have a
pin, V
CC2DET
, or similar, which, indicates to the EZ1900
in which mode to operate. Pin 1 (SEL) of the EZ1900
detects this signal: floating (or open)
indicates single-plane (current shar-
ing) and low switches the outputs for
split-plane operation.
A typical application circuit is shown in
figure 1. The master regulator powers
the CPU core and the slave supplies
the I/O circuitry.
C2
470uF/10V
+
C1
470uF/16V
U1
1
2
R3
33
3
4
MASTER
LP2951CM
INPUT
FEEDBACK
R1
390
Q2
STP8
OUTPUT
SENSE
8
7
6
5
R4
(See Table2)
VCC2
SHUTDOWN 5V TAP
GROUND
ERROR
+
VIN
Current Sharing
The EZ1900 controls current sharing
by sensing the input current to the two
regulators by means of the two sense
resistors, R
15
& R
14
. For balanced cur-
rents, the voltage drop across each
resistor should be of the order of 50 -
100mV [around 10 - 20m鈩? for a 5A
current].
U3
MODE
1
SEL
3
+IN
+V
7 EZ1900
R8
15k
C3 0.1uF
C5
0.1uF
-IN
SOUT -V
2
6
R15
(See Table1)
+
4
C6
470uF/16V
U2
1
2
R12
33
3
4
SLAVE
LP2951CM
INPUT
FEEDBACK
R13
15k
8
7
6
5
R11
(See Table2)
R9
390
Q3
STP8
VIO
OUTPUT
SENSE
SHUTDOWN 5V TAP
GROUND
ERROR
+
C7
C10
0.1uF
0.1uF
C9
470uF/16V
For most split-plane regulators, the
CPU core requires no more than 6A,
with 3A or less for the I/O. The two
regulators will provide enough power
in master-slave mode to power all
versions of the Cyrix 6x86 processor
at 8A or more.
Figure 1: Typical Application Circuit
Pentium is a registered trademark of Intel Corporation; 6x86 is a trademark of Cyrix Corporation; AMD5
K
86 is a trademark of
AMD; PowerPC is a trademark of IBM.
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漏 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
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