CLK A and CLK B respectively. RND,
CLK A and CLK B. TC specifies the input
(TC LOW). RND, when HIGH, adds 鈥?鈥?/div>
to the most significant bit position of the
least significant half of the product. Sub-
The LMA1009/2009 produces the 24-bit
sequent truncation of the 12 least signifi-
product of two 12-bit numbers. The
cant bits produces a result correctly
results of a series of multiplications may
rounded to 12-bit precision.
be accumulated to form the sum of prod-
ucts. Accumulation is performed to The ACC and SUB inputs control accu-
27-bit precision with the multiplier prod- mulator operation. ACC HIGH results in
addition of the multiplier product and
uct sign extended as appropriate.
the accumulator contents, with the result
stored in the accumulator register on the
rising edge of CLK R. ACC and SUB
A
11-0
B
11-0
HIGH results in subtraction of the accu-
12
12
mulator contents from the multiplier
A REGISTER
B REGISTER
product, with the result stored in the
accumulator register. With ACC LOW
and SUB LOW, no accumulation occurs
and the next product is loaded directly
into the accumulator register. ACC LOW
and SUB HIGH is undefined.
The
LMA1009
and
LMA2009
are high-
speed, low power 12-bit multiplier-accu-
mulators. They are pin-for-pin equiva-
lent to the TRW TDC1009/TMC2009
multiplier-accumulators. The LMA1009
and LMA2009 are functionally identical;
they differ only in packaging. Full ambi-
ent temperature range operation is
achieved by the use of advanced CMOS
technology.
24
R
R + A
R 鈥?A
A
27
FEATURES
u
20 ns Multiply-Accumulate Time
u
Low Power CMOS Technology
u
Replaces Fairchild TDC1009/
TMC2009
u
Two鈥檚 Complement or Unsigned
Operands
u
Accumulator Performs Preload,
Accumulate, and Subtract
u
Three-State Outputs
u
68-pin PLCC, J-Lead
LMA1009/2009 B
LOCK
D
IAGRAM
CLK A
CLK B
TC
ACC
SUB
REGISTER
RND
OEX
OEM
OEL
PREL
3
OEX
OEM
OEL
PRELOAD
CONTROL
LOGIC
3
LEX
LEM
LEL
PASS R
The LMA1009/2009 output register (ac-
cumulator register) is divided into three
independently controlled sections. The
least significant result (LSR) and most
significant result (MSR) registers are 12
bits in length. The extended result regis-
ter (XTR) is 3 bits long.
Each output register has an independ-
ent output enable control. In addition
to providing control of the three-state
output buffers, when OEX, OEM, or
OEL are HIGH and PREL is HIGH, data
can be preloaded via the bidirectional
output pins into the respective output
registers. Data present on the output
pins is latched on the rising edge of
CLK R. The interrelation of PREL and
the enable controls is summarized in
Table 1.
LEX
27
3
LEM
12
LEL
12
CLK R
ACCUMULATOR REGISTER
OEX
3
R
26-24
OEM
12
R
23-12
OEL
12
R
11-0
Multiplier-Accumulators
1
03/29/2000鈥揕DS.10/2009-L
1
2
3
4
5
6
7
