LM9648 Color CMOS Image Sensor SXGA 18 FPS
ADVANCE INFORMATION
May 2002
LM9648 Color CMOS Image Sensor SXGA 18 FPS
General Description
The LM9648 is a high performance, low power, 1/2" SX GA
CMOS Active Pixel Sensor capable of capturing color still or
motion images and converting them to a digital data stream.
Mega-pixel class image quality is achieved by integrating a high
performance analog signal processor comprising of a high
speed 10 bit A/D convertor, fixed pattern noise elimination cir-
cuits and separate color gain amplifiers . The offset and black
level can be automatically adjusted on chip using a full loop
black level compensation circuit.
Furthermore, a programmable smart timing and control circuit
allowing the user maximum flexibility in adjusting integration
time, active window size, gain, frame rate. Various control, tim-
ing and power modes are also provided.
Applications
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f
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f
Dual Mode Camera
Digital Still Camera
Security Camera
Machine Vision
Key Specifications
Array Format
Effective Image Area
Optical Format
Pixel Size
Total: 1032 x 1312
Active: 1032 x 1288
Total: 6.30mm x 7.83mm
Active: 6.27mm x 7.81mm
1/2"
6.0碌m x 6.0碌m
8 & 10 Bit Digital
18 frames per second
57 dB
Rolling reset
0.5%
1.7%
2.5 volts/lux.s
49%
Bayer pattern
48 LCC
3.0V +/- 10%
150mW
-10
o
C to 50
o
C
Features
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Video and snapshot operation
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Progressive scan read out with horizontal and vertical flip
f
Programmable Exposure:
- Master clock divider
- Inter row delay
- Inter frame delay
- Partial frame integration
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Four channels of digitally programmable analog gain
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Full automatic servo loop for black level & offset adjustment
on each gain channel
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Horizontal & vertical sub-sampling (2:1 & 4:2) with averaging
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Windowing
f
Programmable pixel clock, inter-frame and inter-line delays
f
compatible serial control interface
f
Power on reset & power down mode
I
2
C
Video Outputs
Frame Rate
Dynamic Range
Shutter
FPN
PRMU
Sensitivity
Fill Factor
Color Mosaic
Package
Single Supply
Power Consumption
Operating Temp
Overall Chip Block Diagram
sclk sda
sadr
resetb
pwd
mclk
APS Array
Row Address
Decoder
Register
Bank
I
2
C Compatible
Serial I/F
POR
Power
Control
clk gen
Master Sensor Controller
snapshot
extsync
Black Level
Compensation
+/-
Horizontal
Register
+/-
+/-
+/-
ch0
ch1
MUX
ch2
ch3
10 bit A/D
Digital V ideo
Framer
d[9:0]
pclk
hsync
vsync
Column CDS
漏
2002 National Semiconductor Corporation
www.national.com
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