LM9618 Monochrome CMOS Image Sensor VGA 30 FPS
ADVANCE INFORMATION
May 2002
LM9618
Monochrome
CMOS Image Sensor VGA 30 FPS
General Description
The LM9618 is a high performance, low power, 1/3鈥?VGA CMOS
Active Pixel Sensor capable of capturing grey-scale digital still or
motion images and converting them to a digital data stream.
In addition to the active pixel array, an on-chip 12 bit A/D conver-
tor, fixed pattern noise elimination circuits, a video gain and sep-
arate color gain are provided. Furthermore, an integrated
programmable smart timing and control circuit allows the user
maximum flexibility in adjusting integration time, active window
size, gain and frame rate. Various control, timing and power
modes are also provided.
The excellent linear dynamic range of the sensor can be
extended to above 100dB by programming a non linear
response curve that matches the response of the human eye.
Applications
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Security Cameras
Machine Vision
Automotive
Biometrics
IR imaging
Barcode Scanners
Key Specifications
Array Format
Effective Image Area
Optical Format
Pixel Size
Video Outputs
Frame Rate
Dynamic Range
Electronic Shutter
FPN
PRMU
Sensitivity
Quantum Efficiency
Fill Factor
Package
Single Supply
Power Consumption
Operating Temp
Total:
664H x 504V
Active: 648H x 488 V
Total: 4.98 mm x 3.78 mm
Active: 4.86 mm x 3.66 mm
1/3鈥?/div>
7.5碌m x 7.5碌m
8,10 & 12 Bit Digital
30 frames per second
62dB in linear mode
110dB in non linear mode
Rolling reset
0.1%
1.5%
5 V/lux.s
27%
47%
48 CLCC
3.3 V +/-10%
120 mW
-40 to 85
o
C
Features
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Video or snapshot operations
Progressive scan and interlace read out modes.
Programmable pixel clock, inter-frame and inter-line delays.
Programmable partial or full frame integration
Programmable gain and individual color gain
Horizontal & vertical sub-sampling (2:1 & 4:2)
Programmable digital video response curve
Windowing
External snapshot trigger & event synchronisation signals
Auto black level compensation
Flexible digital video read-out supporting programmable:
- polarity for synchronisation and pixel clock signals
- leading edge adjustment for horizontal synchronization
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Programmable via 2 wire I
2
C compatible serial interface
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Power on reset & power down mode
Overall Chip Block Diagram
Bad Pixel
Detect & Correct
Horizontal Shift
Register
Column CDS
Black Level
Compensation
R
AMP
G
B
Digital Video
Framer
oe
d[11:0]
pclk
hsync
vsync
Row Address
Decoder
APS Array
POR
Reset
Gen
Vertical
Timing
MUX
12 Bit A/D
Row Address
Gen
Horizontal
Timing
Gain
Control
Register Bank
I
2
C Compatible
Serial I/F
sda
sclk
sadr
Clock Gen
Controller
(sequencer)
Master Timer
Power
Control
reset mclk
extsync
snapshot
pdwn
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2002 National Semiconductor Corporation
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