危鈭?/div>
architecture, followed by a
digital downsampling block and a digital filter, featur-
ing high sensitivity, 800 Hz signal bandwidth and a
complete serial port interface for a direct connection
BLOCK DIAGRAM
to microprocessor environment. An embedded PLL
allows internal clock generation from an external syn-
chronization signal.
SENSOR
A/D
CONVERTER
DIGITAL
FILTER
SER.
IFC
SPE
SPD
SPC
Clk-IN
PLL
D02IN1363
April 2002
This is preliminary information on a new product now in development. Details are subject to change without notice.
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