超碰在线一二三区,亚洲激情四射91国产se

LH6V4256

FUNCTION

鈥?/div>

262,144 words

脳

4 bit

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Access time: 100 ns (MAX)

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Cycle time: 190 ns (MIN)

鈥?/div>

Fast page mode cycle time: 60 ns (MIN)

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Power supply: +3.3 V

鹵0.3

V

鈥?/div>

Power consumption (MAX):

Operating: 126 mW

Standby: 0.54 mW

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Built-in latch circuit for row-address,

column-address, and input data

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OE = Don鈥檛 care in early write operation

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RAS only refresh, hidden refresh, and

CAS before RAS refresh capability

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On-chip refresh counter

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512 refresh cycle/8 ms

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Packages:

20-pin, 300-mil DIP

26-pin, 300-mil SOJ

28-pin, 8

脳

13 mm

2

TSOP (Type I)

CMOS 1M (256K

脳

4) Dynamic RAM

DESCRIPTION

The LH6V4256 is a 262,144 word

脳

4-bit dynamic

RAM which allows fast page mode access. The

LH6V4256 is fabricated on SHARP鈥檚 advanced CMOS

double-level polysilicon gate technology. With its input

multiplexed and packaged in the standard 20-pin DIP,

26-pin SOJ, or 28-pin TSOP (I) packages, it is easy to

realize memory systems with low power dissipation and

large memory capacity. The LH6V4256 operates on a

single +3.3 V power supply and the built-in biasing

voltage generator circuit.

PIN CONNECTIONS

20-PIN DIP

I/O

1

I/O

2

WE

RAS

NC

A

0

A

1

A

2

A

3

V

CC

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

V

SS

I/O

4

I/O

3

CAS

OE

A

8

A

7

A

6

A

5

A

4

6V4256-1

TOP VIEW

Figure 1. Pin Connections for DIP Package

2-14

型號

版本

描述

廠商

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LH6V4256

英文版

CMOS 1M (256K x 4) Dynamic RAM

SHARP

LH6V4256
LH6V4256

英文版

CMOS 1M (256K x 4) Dynamic RAM

SHARP [Sha...

LH6V4256

LH6V4256 Datasheet

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LH6V4256 Datasheet

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