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LH5PV8512 Datasheet

  • LH5PV8512

  • CMOS 4M (512K x 8) Pseudo-Static RAM

  • 12頁(yè)

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LH5PV8512
FEATURES
鈥?/div>
524,288 words
脳
8 bit organization
鈥?/div>
CE access time (t
CEA
): 120 ns (MAX.)
鈥?/div>
Cycle time (t
RC
): 190 ns (MIN.)
鈥?/div>
Power supply:
+3.0 V
鹵
0.15 V (Operating)
+2.2 V to +3.15 V (Data retention)
鈥?/div>
Power consumption (MAX.):
126 mW (Operating)
95
碌W
(Standby = CMOS input level)
221
碌W
(Self-refresh = CMOS input level)
鈥?/div>
Available for address refresh,
auto-refresh, and self-refresh modes
鈥?/div>
2,048 refresh cycles/32 ms
鈥?/div>
Address non-multiple
鈥?/div>
Not designed or rated as radiation
hardened
鈥?/div>
Package:
32-pin, 525-mil SOP
鈥?/div>
Package material: Plastic
鈥?/div>
Substrate material: P-type silicon
鈥?/div>
Process: Silicon-gate CMOS
鈥?/div>
Operating temperature: 0 - 70擄C
CMOS 4M (512K
脳
8) Pseudo-Static RAM
DESCRIPTION
The LH5PV8512 is a 4M bit Pseudo-Static RAM with
a 524,288 word
脳
8 bit organization. It is fabricated
using silicon-gate CMOS process technology.
A PSRAM uses on-chip refresh circuitry with a DRAM
memory cell for pseudo-static operation which elimi-
nates external clock inputs, while having the same
pinout as industry standard SRAMs. Moreover, due to
the functional similariti es between PSRAMs and
SRAMs, existing 512K
脳
8 SRAM sockets can be filled
with the LH5PV8512N with little or no changes. The
advantage is the cost saving realized with the lower
cost PSRAM.
The LH5PV8512 has the ability to fill the gap between
DRAM and SRAM by offering low cost, low power
standby and simple interface.
PIN CONNECTIONS
32-PIN SOP
A
18
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A
15
A
17
WE
A
13
A
8
A
9
A
11
OE/RFSH
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
5PV8512-1
TOP VIEW
Figure 1. Pin Connections
1

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