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LH5PV16256 Datasheet

  • LH5PV16256

  • CMOS 4M (256K x 16) Pseudo-Static RAM

  • 14頁(yè)

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LH5PV16256
FEATURES
鈥?/div>
262,144 words
脳
16 bit organization
鈥?/div>
Power supply: +3.0
鹵
0.15 V
鈥?/div>
Access time: 120 ns (MAX.)
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Cycle time: 190 ns (MIN.)
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Power consumption (MAX.):
126 mW (Operating)
94.5
碌W
(Standby = CMOS input level)
220.5
碌W
(Self-refresh = CMOS input level)
鈥?/div>
LVTTL compatible I/O
鈥?/div>
Available for address refresh,
auto-refresh, and self-refresh modes
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2,048 refresh cycles/32 ms
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Address non-multiple
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Available for byte write mode using UWE
and LWE pins
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Package:
44-pin, TSOP (Type II)
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Process: Silicon-gate CMOS
鈥?/div>
Operating temperature: 0 - 70擄C
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Not designed or rated as radiation
hardened
CMOS 4M (256K
脳
16) Pseudo-Static RAM
DESCRIPTION
The LH5PV16256 is a 4M bit Pseudo-Static RAM with
a 262,144 words
脳
16 bit organization.
PIN CONNECTIONS
44-PIN TSOP (Type II)
TOP VIEW
LWE
UWE
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
17
CS
A
16
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
7
CE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
GND
I/O
15
I/O
14
I/O
13
I/O
12
I/O
11
I/O
10
I/O
9
I/O
8
V
CC
V
CC
RFSH
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
I/O
0
OE
GND
5PV16256S-1
Figure 1. Pin Connections
1

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